DS90LV804 Datasheet, PDF (2/6 Pages) National Semiconductor (TI) – 4-Channel 800 Mbps LVDS Buffer/Repeater

Pin Descriptions
Pin
Name
LLP Pin
Number
I/O, Type
DIFFERENTIAL INPUTS
IN0+
IN0−
9
I, LVDS
10
IN1+
IN1−
11
I, LVDS
12
IN2+
IN2−
13
I, LVDS
14
IN3+
IN3−
15
I, LVDS
16
DIFFERENTIAL OUTPUTS
OUT0+
32
O, LVDS
OUT0−
31
OUT1+
30
O, LVDS
OUT1−
29
OUT2+
28
O, LVDS
OUT2−
27
OUT3+
26
O, LVDS
OUT3-
25
DIGITAL CONTROL INTERFACE
EN
8
I, LVTTL
POWER
V_DD
GND
3, 4, 6, 7, 19, 20,
21, 22
1, 2, 5, 17, 18
(Note 1)
I, Power
I, Power
N/C
23, 24
Description
Channel 0 inverting and non-inverting differential inputs.
Channel 1 inverting and non-inverting differential inputs.
Channel 2 inverting and non-inverting differential inputs.
Channel 3 inverting and non-inverting differential inputs.
Channel 0 inverting and non-inverting differential outputs. (Note 2)
Channel 1 inverting and non-inverting differential outputs. (Note 2)
Channel 2 inverting and non-inverting differential outputs. (Note 2)
Channel 3 inverting and non-inverting differential outputs. (Note 2)
Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in
TRI-STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL level input.
V_DD = 3.3V, ±5%
Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP is
used as the primary GND connection to the device. The DAP is the exposed metal
contact at the bottom of the LLP-32 package. It should be connected to the ground
plane with at least 4 vias for optimal AC and thermal performance. The pin numbers
listed should also be tied to ground for proper biasing.
No Connect
Note 1: Note that for the LLP package the GND is connected thru the DAP on the back side of the LLP package in addition to grounding actual pins on the package
as listed.
Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV804 device have been optimized for
point-to-point backplane and cable applications.
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