DS90CR215_09 Datasheet, PDF (5/18 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz

Symbol
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
Parameter
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
TxCLK IN Period (Figure 6)
TxCLK IN High Time (Figure 6)
TxCLK IN Low Time (Figure 6)
TxIN Setup to TxCLK IN (Figure 6)
TxIN Hold to TxCLK IN (Figure 6)
TxCLK IN to TxCLK OUT Delay @ 25°C,V_CC=3.3V (Figure 8)
Transmitter Phase Lock Loop Set (Figure 10)
Transmitter Powerdown Delay (Figure 14)
Min
10.6
12.8
15
0.35T
0.35T
2.5
0
3
Typ
11.0
13.2
T
0.5T
0.5T
3.7
Max
11.3
13.5
50
0.65T
0.65T
5.5
10
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
Parameter
Min Typ Max Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 3)
2.2
5.0
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 3)
2.2
5.0
ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Note 7)(Figure 17)
f = 40 MHz
1.0
1.4 2.15 ns
RSPos1 Receiver Input Strobe Position for Bit 1
4.5
5.0
5.8
ns
RSPos2 Receiver Input Strobe Position for Bit 2
8.1
8.5 9.15 ns
RSPos3 Receiver Input Strobe Position for Bit 3
11.6 11.9 12.6 ns
RSPos4 Receiver Input Strobe Position for Bit 4
15.1 15.6 16.3 ns
RSPos5 Receiver Input Strobe Position for Bit 5
18.8 19.2 19.9 ns
RSPos6 Receiver Input Strobe Position for Bit 6
22.5 22.9 23.6 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Note 6)(Figure 17)
f = 66 MHz
0.7
1.1
1.4
ns
RSPos1 Receiver Input Strobe Position for Bit 1
2.9
3.3
3.6
ns
RSPos2 Receiver Input Strobe Position for Bit 2
5.1
5.5
5.8
ns
RSPos3 Receiver Input Strobe Position for Bit 3
7.3
7.7
8.0
ns
RSPos4 Receiver Input Strobe Position for Bit 4
9.5
9.9 10.2 ns
RSPos5 Receiver Input Strobe Position for Bit 5
11.7 12.1 12.4 ns
RSPos6 Receiver Input Strobe Position for Bit 6
13.9 14.3 14.6 ns
RSKM
RxIN Skew Margin (Note 5) (Figure 18)
f = 40 MHz
490
ps
f = 66 MHz
400
ps
RCOP
RxCLK OUT Period (Figure 7)
15
T
50
ns
RCOH
RxCLK OUT High Time (Figure 7)
f = 40 MHz
6.0 10.0
ns
f = 66 MHz
4.0
6.1
ns
RCOL
RxCLK OUT Low Time (Figure 7)
f = 40 MHz
10.0 13.0
ns
f = 66 MHz
6.0
7.8
ns
RSRC
RxOUT Setup to RxCLK OUT (Figure 7)
f = 40 MHz
6.5 14.0
ns
f = 66 MHz
2.5
8.0
ns
RHRC
RxOUT Hold to RxCLK OUT (Figure 7)
f = 40 MHz
6.0
8.0
ns
f = 66 MHz
2.5
4.0
ns
RCCD
RxCLK IN to RxCLK OUT Delay (Figure 9)
f = 40 MHz
4.0
6.7
8.0
ns
f = 66 MHz
5.0
6.6
9.0
ns
RPLLS
Receiver Phase Lock Loop Set (Figure 11)
10
ms
RPDD
Receiver Powerdown Delay (Figure 15)
1
μs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference
(both dependent on type/length of cable), and clock jitter less than 250 ps.
Note 6: The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Note 7: The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
5
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