DS90CR215_09 Datasheet, PDF (4/18 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz

Symbol
Parameter
I_CCTW
Transmitter Supply Current Worst Case (with
Loads)
I_CCTZ
Transmitter Supply Current Power Down
RECEIVER SUPPLY CURRENT
I_CCRW Receiver Supply Current Worst Case
I_CCRZ
Receiver Supply Current Power Down
Conditions
R_L = 100Ω,
C_L = 5 pF,
Worst Case Pattern
(Figures 1, 2)
, T_A = −10°C to +70°C
R_L = 100Ω,
C_L = 5 pF,
Worst Case Pattern
f = 32.5 MHz
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
(Figures 1, 2)
, T_A = −40°C to +85°C
PWR DWN = Low
Driver Outputs in TRI-STATE
under Powerdown Mode
C_L = 8 pF,
Worst Case Pattern
f = 32.5 MHz
f = 37.5 MHz
(Figures 1, 3)
f = 66 MHz
, T_A = −10°C to +70°C
C_L = 8 pF,
Worst Case Pattern
f = 40 MHz
f = 66 MHz
(Figures 1, 3)
, T_A = −40°C to +85°C
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
Min Typ Max Units
31 45 mA
32 50 mA
37 55 mA
38 51 mA
42 55 mA
10 55 μA
49 65 mA
53 70 mA
78 105 mA
55 82 mA
78 105 mA
10 55 μA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25°C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_OD and ΔV_OD).
Note 4: V_OS previously referred as V_CM.
Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (Figure 2)
0.5
1.5
ns
LHLT
LVDS High-to-Low Transition Time (Figure 2)
0.5
1.5
ns
TCIT
TxCLK IN Transition Time (Figure 4)
5
ns
TCCS
TxOUT Channel-to-Channel Skew (Figure 5)
250
ps
TPPos0 Transmitter Output Pulse Position for Bit0 f = 40 MHz
−0.4
0
(Note 7) (Figure 16)
0.4
ns
TPPos1 Transmitter Output Pulse Position for Bit1
3.1
3.3
4.0
ns
TPPos2 Transmitter Output Pulse Position for Bit2
6.5
6.8
7.6
ns
TPPos3 Transmitter Output Pulse Position for Bit3
10.2
10.4
11.0
ns
TPPos4 Transmitter Output Pulse Position for Bit4
13.7
13.9
14.6
ns
TPPos5 Transmitter Output Pulse Position for Bit5
17.3
17.6
18.2
ns
TPPos6 Transmitter Output Pulse Position for Bit6
21.0
21.2
21.8
ns
TPPos0 Transmitter Output Pulse Position for Bit0 f = 66 MHz
−0.4
0
(Note 6) (Figure 16)
0.3
ns
TPPos1 Transmitter Output Pulse Position for Bit1
1.8
2.2
2.5
ns
TPPos2 Transmitter Output Pulse Position for Bit2
4.0
4.4
4.7
ns
TPPos3 Transmitter Output Pulse Position for Bit3
6.2
6.6
6.9
ns
TPPos4 Transmitter Output Pulse Position for Bit4
8.4
8.8
9.1
ns
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