DS90CR215_09 Datasheet, PDF (13/18 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz

Pin Name
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O No.
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
I 1 Power supply for PLL.
1 2 Ground pin for PLL.
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon the
application the interconnecting media may vary. For example,
for lower data rate (clock rate) and shorter cable lengths (<
2m), the media electrical performance is less critical. For
higher speed/long distance applications the media's perfor-
mance becomes more critical. Certain cable constructions
provide tighter skew (matched electrical length between the
conductors and pairs). Twin-coax for example, has been
demonstrated at distances as great as 5 meters and with the
maximum data transfer of 1.38 Gbit/s. Additional applications
information can be found in the following National Interface
Application Notes:
AN = ####
AN-1041
AN-1035
AN-806
AN-905
AN-916
Topic
Introduction to Channel Link
PCB Design Guidelines for LVDS and
Link Devices
Transmission Line Theory
Transmission Line Calculations and
Differential Impedance
Cable Information
CABLES
A cable interface between the transmitter and receiver needs
to support the differential LVDS pairs. The 21-bit CHANNEL
LINK chipset (DS90CR215/216) requires four pairs of signal
wires and the 28-bit CHANNEL LINK chipset
(DS90CR285/286) requires five pairs of signal wires. The ide-
al cable/connector interface would have a constant 100Ω
differential impedance throughout the path. It is also recom-
mended that cable skew remain below 150 ps (@ 66 MHz
clock rate) to maintain a sufficient data sampling window at
the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the trans-
mitter and receiver. This low impedance ground provides a
common mode return path for the two devices. Some of the
more commonly used cable types for point-to-point applica-
tions include flat ribbon, flex, twisted pair and Twin-Coax. All
are available in a variety of configurations and options. Flat
ribbon cable, flex and twisted pair generally perform well in
short point-to-point applications while Twin-Coax is good for
short and long applications. When using ribbon cable, it is
recommended to place a ground line between each differen-
tial pair to act as a barrier to noise coupling between adjacent
pairs. For Twin-Coax cable applications, it is recommended
to utilize a shield on each cable pair. All extended point-to-
point applications should also employ an overall shield sur-
rounding all cable pairs regardless of the cable type. This
overall shield results in improved transmission parameters
such as faster attainable speeds, longer distances between
transmitter and receiver and reduced problems associated
with EMS or EMI.
Description
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT
To obtain the maximum benefit from the noise and EMI re-
ductions of LVDS, attention should be paid to the layout of
differential lines. Lines of a differential pair should always be
adjacent to eliminate noise interference from other signals
and take full advantage of the noise canceling of the differ-
ential signals. The board designer should also try to maintain
equal length on signal traces for a given differential pair. As
with any high speed design, the impedance discontinuities
should be limited (reduce the numbers of vias and no 90 de-
gree angles on traces). Any discontinuities which do occur on
one signal line should be mirrored in the other line of the dif-
ferential pair. Care should be taken to ensure that the differ-
ential trace impedance match the differential impedance of
the selected physical media (this impedance should also
match the value of the termination resistor that is connected
across the differential pair at the receiver's input). Finally, the
location of the CHANNEL LINK TxOUT/RxIN pins should be
as close as possible to the board edge so as to eliminate ex-
cessive pcb runs. All of these considerations will limit reflec-
tions and crosstalk which adversely effect high frequency
performance and EMI.
UNUSED INPUTS
All unused inputs at the TxIN inputs of the transmitter must
be tied to ground. All unused outputs at the RxOUT outputs
of the receiver must then be left floating.
TERMINATION
Use of current mode drivers requires a terminating resistor
across the receiver inputs. The CHANNEL LINK chipset will
normally require a single 100Ω resistor between the true and
complement lines on each differential pair of the receiver in-
put. The actual value of the termination resistor should be
selected to match the differential mode characteristic
impedance (90Ω to 120Ω typical) of the cable. Figure 19
shows an example. No additional pull-up or pull-down resis-
tors are necessary as with some other differential technolo-
gies such as PECL. Surface mount resistors are recommend-
ed to avoid the additional inductance that accompanies
leaded resistors. These resistors should be placed as close
as possible to the receiver input pins to reduce stubs and ef-
fectively terminate the differential lines.
13
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