DS90CR215_09 Datasheet, PDF (14/18 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz

FIGURE 19. LVDS Serialized Link Termination
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DECOUPLING CAPACITORS
Bypassing capacitors are needed to reduce the impact of
switching noise which could limit performance. For a conser-
vative approach three parallel-connected decoupling capaci-
tors (Multi-Layered Ceramic type in surface mount form
factor) between each V_CC and the ground plane(s) are rec-
ommended. The three capacitor values are 0.1 μF, 0.01μF
and 0.001 μF. An example is shown in Figure 20. The de-
signer should employ wide traces for power and ground and
ensure each capacitor has its own via to the ground plane. If
board space is limiting the number of bypass capacitors, the
PLL V_CC should receive the most filtering/bypassing. Next
would be the LVDS V_CC pins and finally the logic V_CC pins.
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FIGURE 20. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER
The CHANNEL LINK devices employ a PLL to generate and
recover the clock transmitted across the LVDS interface. The
width of each bit in the serialized LVDS data stream is one-
seventh the clock period. For example, a 66 MHz clock has a
period of 15 ns which results in a data bit width of 2.16 ns.
Differential skew (Δt within one differential pair), interconnect
skew (Δt of one differential pair to another) and clock jitter will
all reduce the available window for sampling the LVDS serial
data streams. Care must be taken to ensure that the clock
input to the transmitter be a clean low noise signal. Individual
bypassing of each V_CC to ground will minimize the noise
passed on to the PLL, thus creating a low jitter LVDS clock.
These measures provide more margin for channel-to-channel
skew and interconnect skew as a part of the overall jitter/skew
budget.
COMMON MODE vs. DIFFERENTIAL MODE NOISE
MARGIN
The typical signal swing for LVDS is 300 mV centered at
+1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of differ-
ential noise margin. Common mode protection is of more
importance to the system's operation due to the differential
data transmission. LVDS supports an input voltage range of
Ground to +2.4V. This allows for a ±1.0V shifting of the center
point due to ground potential differences and common mode
noise.
POWER SEQUENCING AND POWERDOWN MODE
Outputs of the CNANNEL LINK transmitter remain in TRI-
STATE until the power supply reaches 2V. Clock and data
outputs will begin to toggle 10 ms after V_CC has reached 3V
and the Powerdown pin is above 1.5V. Either device may be
placed into a powerdown mode at any time by asserting the
Powerdown pin (active low). Total power dissipation for each
device will decrease to 5 μW (typical).
The CHANNEL LINK chipset is designed to protect itself from
accidental loss of power to either the transmitter or receiver.
If power to the transmit board is lost, the receiver clocks (input
and output) stop. The data outputs (RxOUT) retain the states
they were in when the clocks stopped. When the receiver
board loses power, the receiver inputs are shorted to V _CC
through an internal diode. Current is limited (5 mA per input)
by the fixed current mode drivers, thus avoiding the potential
for latchup when powering the device.
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