COP424C Datasheet, PDF (5/24 Pages) National Semiconductor (TI) – Single-Chip 1k and 2k CMOS Microcontrollers

COP324C COP325C COP326C and COP344C COP345C
AC Electrical Characteristics b40 C^sT_A^sa85 C unless otherwise specified
Parameter
Conditions
Min
Max
Units
Instruction Cycle Time (tc)
Operating CKI
Frequency
d4 mode
( ^{d8 mode}
d16 mode
d4 mode
( ^{d8 mode}
d16 mode
V_CC^t4 5V
4 5V^lV_CC^t3 0V
V_CC^t4 5V
4 5V^lV_CC^t3 0V
4
DC
ms
16
DC
ms
DC
10
MHz
DC
20
MHz
DC
40
MHz
DC
250
kHz
DC
500
kHz
DC
10
MHz
Duty Cycle (Note 4)
Rise Time (Note 4)
Fall Time (Note 4)
Instruction Cycle Time
RC Oscillator (Note 4)
f₁e4 MHz
f₁e4 MHz external clock
f₁e4 MHz external clock
R e 30k g5% V_CC e 5V
C e 82 pF g5% (d4 Mode)
40
60
%
60
ns
40
ns
5
11
ms
Inputs (See Figure 3 )
t_SETUP
t_HOLD
G Inputs
tc 4a 7
ms
( ^{SI Inputs}
All Others
V_CC^t 4 5V
03
17
ms
ms
V_CC^t 4 5V
4 5V^lV_CC^t3 0V
0 25
ms
10
ms
Output Propagation Delay
t_PD1 t_PD0
t_PD1 t_PD0
V_OUTe1 5V C_Le100 pF R_Le5k
V_CC^t 4 5V
4 5V^lV_CC^t3 0V
10
ms
40
ms
Microbus Timing
Read Operation (Figure 4 )
Chip Select Stable before RD bt_CSR
Chip Select Hold Time for RD bt_RCS
RD Pulse Widthbt_RR
Data Delay from RD bt_RD
RD to Data Floating bt_DF (Note 4)
C_Le50 pF V_CCe5Vg5%
65
ns
20
ns
400
ns
375
ns
250
ns
Write Operation (Figure 5 )
Chip Select Stable before WR bt_CSW
Chip Select Hold Time for WR bt_WCS
WR Pulse Widthbt_WW
Data Set-Up Time for WR bt_DW
Data Hold Time for WR bt_WD
INTR Transition Time from WR bt_WI
65
ns
20
ns
400
ns
320
ns
100
ns
700
ns
Note 1 Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI CKO open and all other pins pulled up to V_CC with 5k
resistors See current drain equation on page 17
Note 2 The HALT mode will stop CKI from oscillating in the RC and crystal configurations Test conditions all inputs tied to V_CC L lines in TRI-STATE mode and
tied to ground all outputs low and tied to ground
Note 3 When forcing HALT current is only needed for a short time (approx 200 ns) to flip the HALT flip-flop
Note 4 This parameter is only sampled and not 100% tested Variation due to the device included
Note 5 Voltage change must be less than 0 5 volts in a 1 ms period
Note 6 SO output sink current must be limited to keep V_OL less than 0 2V_CC when part is running in order to prevent entering test mode
5