COP424C Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – Single-Chip 1k and 2k CMOS Microcontrollers

Instruction Set (Continued)
Mnemonic Operand ^Hex
Code
Table III COP444C 445C Instruction Set (Continued)
Machine
Language
Code
(Binary)
Data Flow
Skip
Conditions
TRANSFER CONTROL INSTRUCTIONS
JID
FF 1111 1111
JMP
JP
a
6b 0110 0 a_{10 8}
bb
a_{7 0}
a
bb 1 a_{6 0}
(pages 2 3 only)
or
bb 11 a_{5 0}
(all other pages)
x ROM (PC_{10 8} A M) PC_{7 0}
axPC
x a PC_{6 0}
x a PC_{5 0}
None
None
None
JSRP
JSR
RET
a
bb 10 a_{5 0}
PCa1xSAxSBxSC
x 00010 PC_{10 6}
x a PC_{5 0}
None
a
x x x 6b 0110 1 a_{10 8} PCa1 SA SB SC None
bb
a_{7 0}
axPC
48 0100 1000
SCxSBxSAxPC
None
RETSK
HALT
IT
49 0100 1001
33 0011 0011
38 0011 1000
33 0011 0011
39 0011 1001
SCxSBxSAxPC
Always Skip
on Return
None
None
MEMORY REFERENCE INSTRUCTIONS
CAMT
33 0011 0011
3F 0011 1111
CTMA
33 0011 0011
2F 0010 1111
CAMQ
33 0011 0011
3C 0011 1100
CQMA
33 0011 0011
2C 0010 1100
LD
r
b5 00 r 0101
(re0 3)
LDD
rd
23 0010 0011
bb 0 r d
LQID
BF 1011 1111
RMB
SMB
0
4C 0100 1100
1
45 0100 0101
2
42 0100 0010
3
43 0100 0011
0
4D 0100 1101
1
47 0100 0111
2
46 0100 0110
3
4B 0100 1011
x A T_{7 4}
x RAM(B) T_{3 0}
x T_{7 4} RAM(B)
x T_{3 0} A
x A Q_{7 4}
x RAM(B) Q_{3 0}
x Q_{7 4} RAM(B)
x Q_{3 0} A
RAM(B)xA
x Br Z r Br
x RAM(r d) A
x ROM(PC_{10 8} A M) Q
SBxSC
x 0 RAM(B)₀
x 0 RAM(B)₁
x 0 RAM(B)₂
x 0 RAM(B)₃
x 1 RAM(B)₀
x 1 RAM(B)₁
x 1 RAM(B)₂
x 1 RAM(B)₃
None
None
None
None
None
None
None
None
None
Description
Jump Indirect (Notes 1 3)
Jump
Jump within Page (Note 4)
Jump to Subroutine Page
(Note 5)
Jump to Subroutine
Return from Subroutine
Return from Subroutine
then Skip
HALT Processor
IDLE till Timer
Overflows then Continues
Copy A RAM to T
Copy T to RAM A (Note 9)
Copy A RAM to Q
Copy Q to RAM A
Load RAM into A
Exclusive-OR Br with r
Load A with RAM pointed
to directly by r d
Load Q Indirect (Note 3)
Reset RAM Bit
Set RAM Bit
14