CP3CN23 Datasheet, PDF (44/246 Pages) National Semiconductor (TI) – CP3CN23 Reprogrammable Connectivity Processor with Dual CAN Interfaces

Table 18 DMA Controller Registers
Name
ADCA2
ADRA2
ADCB2
Address
FF F840h
FF F844h
FF F848h
Description
Device A Address
Counter Register
Device A Address
Register
Device B Address
Counter Register
9.6.2 Device A Address Register (ADRAn)
The Device A Address register is a 32-bit, read/write regis-
ter. It holds the 24-bit starting address of either the next
source data block, or the next destination data area, according
to the DIR bit in the DMACNTLn register. The upper 8 bits of
the ADRAn register are reserved and always clear.
31 24 23
0
Reserved
Device A Address
ADRB2
BLTC2
BLTR2
DMACNTL2
DMASTAT2
ADCA3
ADRA3
FF F84Ch
FF F850h
FF F854h
FF F85Ch
FF F85Eh
FF F860h
FF F864h
Device B Address
Register
Block Length
Counter Register
Block Length Register
DMA Control Register
DMA Status Register
Device A Address
Counter Register
Device A Address
Register
9.6.3 Device B Address Counter Register (ADCBn)
The Device B Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item, or the destination location, according to
the DIR bit in the CNTLn register. The ADCBn register is up-
dated after each transfer cycle by INCB field of the
DMACNTLn register according to ADB bit of the
DMACNTLn register. In direct (flyby) mode, this register is
not used. The upper 8 bits of the ADCBn register are re-
served and always clear.
31 24
Reserved
23
0
Device B Address Counter
ADCB3
ADRB3
BLTC3
BLTR3
FF F868h
FF F86Ch
FF F870h
FF F874h
Device B Address
Counter Register
Device B Address
Register
Block Length
Counter Register
Block Length Register
9.6.4 Device B Address Register (ADRBn)
The Device B Address register is a 32-bit, read/write regis-
ter. It holds the 24-bit starting address of either the next
source data block or the next destination data area, accord-
ing to the DIR bit in the CNTLn register. In direct (flyby)
mode, this register is not used. The upper 8 bits of the AD-
CRBn register are reserved and always clear.
DMACNTL3
FF F87Ch DMA Control Register
31 24 23
0
DMASTAT3
FF F87Eh DMA Status Register
Reserved
Device B Address
9.6.1 Device A Address Counter Register (ADCAn)
The Device A Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item or the destination location, depending on
the state of the DIR bit in the CNTLn register. The ADA bit
of DMACNTLn register controls whether to adjust the point-
er in the ADCAn register by the step size specified in the
INCA field of DMACNTLn register. The upper 8 bits of the
ADCAn register are reserved and always clear.
9.6.5 Block Length Counter Register (BLTCn)
The Block Length Counter register is a 16-bit, read/write
register. It holds the current number of DMA transfers to be
executed in the current block. BLTCn is decremented by one
after each transfer cycle. A DMA transfer may consist of 1 or
2 bytes, as selected by the DMACNTLn.TCS bit.
15
0
31 24 23
Block Length Counter
0
Reserved
Device A Address Counter
Note: 0000h is interpreted as 2¹⁶-1 transfer cycles.
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