CP3CN23 Datasheet, PDF (123/246 Pages) National Semiconductor (TI) – CP3CN23 Reprogrammable Connectivity Processor with Dual CAN Interfaces

18.6.4 IOM-2 Mode
The AAI can operate in a special IOM-2 compatible mode to
allow to connect to an external ISDN controller device. In
this IOM-2 mode, the AAI can only operate as a slave, i.e.
the bit clock and frame sync signal is provided by the ISDN
controller. The AAI only supports the B1 and B2 data of the
IOM-2 channel 0, but ignores the other two IOM-2 channels.
The AAI handles the B1 and B2 data as one 16-bit data
word.
The IOM-2 interface has the following properties:
„ Bit clock of 1536 kHz (output from the ISDN controller)
„ Frame repetition rate of 8 ksps (output from the ISDN
controller)
„ Double-speed bit clock (one data bit is two bit clocks
wide)
„ B1 and B2 data use 8-bit log PCM format
„ Long frame sync pulse
Figure 55 shows the structure of an IOM-2 Frame.
SFS
STD/SRD
B1 B2 M C IC1 IC2 M C
C
IOM-2 Channel 0
IOM-2 Channel 1
IOM-2 Channel 2
IOM-2 Frame (125 µs)
DS162
Figure 55. IOM-2 Frame Structure
Figure 56 shows the connections between an ISDN control-
ler and a CP3CN23 using a standard IOM-2 interface for the
B1/B2 data communication and the external bus interface
(IO Expansion) for controlling the ISDN controller.
SCK
CP3BT2x
SFS
STD
SRD
A[7:0]
Bit Clock
Frame Sync
ISDN Controller
Data In
Data Out
Address
To connect the AAI to an ISDN controller through an IOM-2
compatible interface, the AAI needs to be configured in this
way:
„ The AAI must be in IOM-2 Mode (AGCR.IOM2 = 1).
„ The AAI operates in synchronous mode (AGCR.ASS =
0).
„ The AAI operates as a slave, therefore the bit clock and
frame sync source selection must be set to external
(ACGR.IEFS = 1, ACGR.IEBC = 1).
„ The frame sync length must be set to long frame sync
(ACGR.FSS = 1).
„ The data word length must be set to 16-bit (AGCR.DWL
= 1).
„ The AAI must be set to normal mode (AGCR.SCS[1:0] =
0).
„ The internal frame rate must be 8 ksps (ACCR = 00BE).
D[7:0]
Data
18.6.5 Loopback Mode
SELIO
RD
Chip Select
Output Enable
DS241
In loopback mode, the STD and SRD pins are internally
connected together, so data shifted out through the ATSR
register will be shifted into the ARSR register. This mode
may be used for development, but it also allows testing the
transmit and receive path without external circuitry, for ex-
ample during Built-In-Self-Test (BIST).
Figure 56. CP3CN23/ISDN Controller Connections
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