CP3CN23 Datasheet, PDF (227/246 Pages) National Semiconductor (TI) – CP3CN23 Reprogrammable Connectivity Processor with Dual CAN Interfaces

SDA
0.7VCC
0.3VCC
0.7VCC
0.3VCC
0.7VCC
SCL
0.3VCC
t_SDAr
t_SDAf
0.7VCC
0.3VCC
t_SCLr
t_SCLf
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing.
DS106
Figure 107. ACB Signals (SDA and SCL) Timing
Stop Condition
Start Condition
SDA
SCL
t_DLCs
t_CSTOs
t_BUF
t_CSTRh
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing.
Figure 108. ACB Start and Stop Condition Timing
DS107
SDA
Start Condition
SCL
t_DHCs
t_CSTRs
t_CSTRh
Note: In the timing tables the parameter name is added with an "o" for output signal timing
and "i" for input signal timing.
DS108
Figure 109. ACB Start Condition Timing
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