DS92LV3241_10 Datasheet, PDF (4/6 Pages) National Semiconductor (TI) – Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des

them to interface with heavy input capacitance loads found
on many ASIC and FPGA devices. In addition, the LVCMOS
data busses of the serializer and deserializer can be inde-
pendently controlled to latch data out on either the rising or
falling clock edge to accommodate the interface of the host
devices.
New systems can maintain a simple start up sequence, be-
cause the deskew process is integrated into the locking se-
quence and requires no external device manipulation. Unlike
other devices with deskew circuits, a DS92LV3241 and
DS92LV3242 system need only apply parallel clock and data
to the serializer to begin data transmission while properly
deskewing the interconnect.
The improved architecture of the DS92LV3241 and
DS92LV3242 from first generation Channel Link devices,
means that designers no longer have to worry about calcu-
lating RSKM down to the tens of picoseconds. Jitter transfer
characteristics are provided for the serializer’s phase locked
loop (PLL), while input jitter tolerance characteristics are pro-
vided for the deserializer’s clock and data recovery modules
(CDR). In addition, the method of deskew was improved from
the 48-bit versions of Channel Link devices to deskew input
serial streams relative to the parallel clock frequency. This
allows interconnects to now have greater amounts of inter-
pair skew without compromising the integrity of the serial link.
Summary
Features such as automatic deskew, transmit pre-emphasis,
selectable V_OD, data encoding and dc balancing make the
DS92LV3241/DS92LV3242 Channel Link II Ser/Des devices
well suited for Imaging, Machine Vision, and Display applica-
tions. These features allow for more robust serial connections
and greatly simplify the design in process over the previous
generation of Channel Link products.
Note 1: RSKM Min Value = 290ps, DS90CR287/DS90CR288A Datasheet July 2004. Receiver Skew Margin is defined as the valid data sampling region at the
receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling
window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and source clock (less than
150 ps).
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