DS92LV3241_10 Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des

New Features in Channel Link II Ser/
Des
SELECTABLE V_OD
The output differential voltage swing of the DS92LV3241 and
DS92LV3221 can be altered by setting the VSEL pin to LOW
for ±220 mV (440 mV_P-P), or HIGH for ±425 mV (850 mV_P-P).
The low swing option consumes less power. However, the
large swing option allows for further cable reach. Pre-Em-
phasis can be used with both V_OD settings to help achieve
better cable performance, while consuming little additional
power.
PRE-EMPHASIS
Pre-Emphasis can help to compensate for long or lossy trans-
mission lines by proving added current to the higher frequen-
cy portions of the transmitted data. The amount of current
added is related to the resistor which is attached to the PRE
pin to ground (V_SS) by the following equations 1 below. Equa-
tion 2, shows how the added current corresponds to a boost
in the V_OD
I_PRE = 48 / R_PRE
(1)
V_ODPRE = I_PRE x 50 Ω
(2)
The minimum recommended value for RPRE is 12 kΩ. If no
pre-emphasis is required the PRE pin should be left floating.
If pre-emphasis is not expected to be used for a design, it is
still recommended to place the pads for a resistor to connect
the PRE pin to V_SS on the PCB. A simple note to designate
“Do Not Populate” the resistor at board assembly allows the
serializer to meet existing system requirements, while also
allowing the same PCB to be used in future systems which
require longer cable lengths.
AT-SPEED BIST
The AT-SPEED BIST allows users to observe the quality of
their link in terms of measured bit errors. In order to use the
AT-SPEED BIST the transmitter, DS92LV3241/
DS92LV3221, must have both a valid TxCLKIN and the BIS-
TEN pin must be pulled HIGH. The receiving device must
obtain lock before it can report out the status of the BIST.
During BIST mode, the serializer will ignore data on the TxIN
pins and instead transmit out a balanced and encoded pseu-
do random bit sequence. The deserializer will automatically
detect the incoming BIST pattern and enter BIST mode. While
the deserializer is in BIST mode, the RXOUT pins will be re-
assigned to report out BIST status , pass or fail, and an error
count for each high speed serial channel.
The AT-SPEED BIST can be used to speed up the design and
validation process, by allowing designers to validate the sig-
nal integrity of the serial links. For detailed information on how
to use the AT-SPEED BIST, please consult Functional De-
scription section of the applicable datasheets.
DESKEW
Deskew is performed automatically on the serial links during
the deserializer lock process. The deserializer does not re-
quire a special deskew procedure, nor any special deskew
patterns. During lock acquisition, a clock is recovered from
each serial channel. These clocks are then used to align the
decoded and deserialized data relative to clock recovered on
channel 0. As shown in Table 1, the deskew circuit allows the
maximum tolerable skew length to increase from the hun-
dreds of picoseconds for Channel Link devices to nanosec-
onds for Channel Link II devices.
DC-BALANCED AND ENCODED DATA
The parallel data is processed is 3 ways before being serial-
ized and transmitted out onto the serial channel. First the data
is scrambled and then DC Balanced. The DC-Balanced data
then goes through a bit shuffle circuit which manages the
emissions of the serial stream by controlling the number of
transitions per serial word. By the time the parallel data is
ready to be transmitted out on the serial channel, 4 additional
bits have been appended on. The first and last bits of each
word are commonly referred to as clock bits. These bits are
set at a static value, one HIGH and one LOW. This guarantees
that there will always be at a minimum one transition for every
serial word.
Using Channel Link II Devices to
Improve Old and New Designs
First Generation Channel Link devices allowed users to trans-
mit 24-bit color with H-sync(HS), V-sync(VS) and Data Enable
(DE), while leaving only one spare bit for other control signals.
The 32 bit wide parallel bus of the DS92LV3241/DS92LV3242
allows for a total of 5 additional control signals to be trans-
mitted along with the 24 color and 2-sync and enable bits.
These 5 added bits can be used to transmit triggers or other
control data on the same wire pairs as the video data, unlike
previous generation system which required additional com-
ponents and wires to transmit this information. Also, the wide
data bus now allows for 10-bit color application with 2 bits left
for sync signals or data enable.
The integrated transmit signal conditioning allows designers
to transmit data over longer distances or use less expensive
lossy cables. The automatic deskew circuit also allows the
use of more commercially available cables with less stringent
skew requirements, such as CAT-5/6.
The automatic deskew circuit allows for a simple start se-
quence, while enabling cable lengths that were not possible
in earlier generation systems. For example, many industrial
imaging or machine vision applications use of mini-delta-rib-
bon (MDR) cable to transport the serial imaging data, be-
cause of their relatively tight inter-pair skew specifications
which varied from 50 – 100+ ps/m depending on the cable
vendor. In first generation Channel Link systems, one of the
most critical parameters, RSKM, was dominated by intercon-
nect skew. The minimum RSKM at 85 MHz, was specified to
be 290 ps. If it is assumed that cable skew dominates RSKM,
then at 85 MHz with a high quality MDR cable, the expected
cable length performance would max out at 290 ps / (50 ps/
m) = 5.8m, neglecting any degradation in performance due to
the insertion loss of the cable. With the DS92LV3241/
DS92LV3242 chipset, the system would be capable of 0.4 x
(1 / 85 MHz) = 4.71 ns of cable skew. If a similar quality MDR
cable is used, then the system could handle cables of 4.71
ns / (50 ps/m) = 94.2m, again neglecting any degradation in
performance due to the insertion loss of the cable.
Using Channel Link II devices to
Simplify New Designs
The DS92LV3241/DS92LV3242 were designed to ease the
learning curve burden of system designers and to maintain
“ease of use.”
The DS92LV3241 can be configured to accept either 1.8V or
3.3V LVCMOS logic levels. This allows the serializer to easily
interface to a variety of host devices without the need for input
buffers or logic level shifters. The LVCMOS drivers found on
the DS92LV3242 are capable of driving 8pF load, allowing
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