DS92LV3241_10 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des

Improving the Robustness
of Channel Link Designs
with Channel Link II Ser/Des
National Semiconductor
Application Note 2007
Michael Wolfe
February 17, 2010
Introduction
The first generation Channel Link Ser/Des devices allowed
system designers to transmit a wide data bus while reducing
their interconnect density. These devices used a parallel
clock architecture which eliminated the need for local refer-
ence oscillators and training/synchronization patterns to ob-
tain lock in the receive system. These unique features allowed
devices such as the DS90CR217/218A, DS90CR285/286A
and the DS90CR287/288A to become very popular in the in-
dustrial imaging, printing and digital video transport markets.
As technology advanced in display and sensor resolution, in-
terconnect distance requirements also increased. Since, the
first generation Channel Link devices used a parallel clock
architecture to transmit serial data, system designers had to
closely monitor the inter-pair (channel-to-channel) skew
specifications of their interconnects and in turn, the overall
receiver skew margin (RSKM).
The new Channel Link II Ser/Des family of products tackles
these limiting older system specifications with new and inno-
vative architectural changes. All Channel Link II Ser/Des use
an embedded clock architecture with encoded data. This al-
lows Channel Link II receivers to lock on to random data
transmitted through an AC-coupled interfaces with minimal
interconnect density and no reference clocks or oscillators. In
addition, the thermal tolerance of all Channel Link II Ser/Des
was improved to operate within the industrial temperature
range of -40°C to +85°C.
Channel Link II Ser/Des
DS92LV3241/DS92LV3242 20 MHz – 85 MHz, 32 Bit
LVCMOS Ser/Des with Automatic Deskew and Transmit
Pre-Emphasis
The DS92LV3241/DS92LV3242 Ser/Des chipset can trans-
port up to 32 bits of parallel data at rates of 20 MHz to 85 MHz
across 2 (dual mode) or 4 (quad mode) serial data lanes. An
integrated deskew circuit, compensates for the inter-pair
skew up to 0.4 x transmit clock period (t_CIP). The deskew pro-
cess is transparent to the system and is performed automat-
ically during the locking sequence of the deserializer. The
serializer has a selectable output differential voltage swing
(V_OD) and configurable transmit pre-emphasis block to help
compensate for high frequency attenuation across the serial
interconnects. These three key specifications allow the
DS92LV3241/DS92LV3242 to transmit more data, through
less expensive interconnects and across longer distances
that the first generation of Channel Link Ser/Des.
For systems that do not require the full 20 MHz – 85 MHz
bandwidth, there is also a pin compatible chipset, the
DS92LV3221/DS92LV3222. This chipset operates only in the
2 lane (dual mode) configuration with an operating frequency
range of 20 MHz – 50 MHz. The DS92LV3221 and
DS92LV3222 contain all of the key specifications of their quad
lane capable counterparts such as: automatic deskew, se-
lectable V_OD, configurable transmit pre-emphasis and inte-
grated AT-SPEED BIST.
A side by side comparison of several Channel Link devices
and Channel Link II devices is shown in Table 1.
FIGURE 1. DS92LV3241/DS92LV3242 Block Diagram
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