DS92LV3241_10 Datasheet, PDF (2/6 Pages) National Semiconductor (TI) – Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des

TABLE 1. Channel Link vs. Channel Link II Feature Set Comparison
Channel Link
Channel Link II
Chipset (Ser/Des) DS90CR217/218A DS90CR285/286A DS90CR287/288A DS92LV3221/3222 DS92LV3241/3242
Serialization Ratio
21 : 4
28 : 5
28 : 5
32 : 2
(3 Data + 1 Parallel (4 Data + 1 Parallel (4 Data + 1 Parallel (2 Lanes with
Clock)
Clock)
Clock)
Embedded Clock)
32 : 2/4
(2 or 4 Lanes with
Embedded Clock)
Frequency Range
(MHz)
20 – 85
20 – 66
20 – 85
20 – 50
20 – 85
Parallel Data Bus
Width
21 Bit
28 Bit
28 Bit
32 Bit
32 Bit
Max Total
Throughput (Gbps)
1.785
1.848
2.38
1.6
2.72
Operating
-10°C to +70°C
Temperature Range
-40°C to +85°C
-10°C to +70°C -40°C to +85°C
-40°C to +85°C
Maximum Skew
Tolerance (min
RSKM) at f_MAX
Automatic Deskew
490 ps
(f = 85 MHz)
No
400 ps
(f = 66 MHz)
No
290 ps
(f = 85 MHz)
No
8.0 ns
(f = 50 MHz)
Yes
4.7 ns
(f = 85 MHz)
Yes
DC Balanced and
Encoded Data
No
No
No
Yes
Yes
AT-SPEED BIST
No
No
No
Yes
Yes
Configurable
Transmit Pre-
No
No
No
Yes
Yes
Emphasis
Selectable V_OD
No
No
No
Yes
Yes
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