DS90C385 Datasheet, PDF (4/17 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) L

Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figures 13, 14)
(Note 5)
f = 85 MHz
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TSTC TxIN Setup to TxCLK IN (Figure 7)
THTC TxIN Hold to TxCLK IN (Figure 7)
TCCD TxCLK IN to TxCLK OUT Delay (Figure 8)
T_A = 25˚C, V_CC =
3.3V
TxCLK IN to TxCLK OUT Delay (Figure 8)
TJCC
Transmitter Jitter Cycle-to-Cycle (Figures 15, 16) (Note 6)
f = 85 MHz
f = 65 MHz
f = 40 MHz
TPLLS Transmitter Phase Lock Loop Set (Figure 9)
TPDD Transmitter Power Down Delay (Figure 12)
Min Typ
−0.20 0
Max Units
0.20 ns
1.48 1.68 1.88 ns
3.16 3.36 3.56 ns
4.84 5.04 5.24 ns
6.52 6.72 6.92 ns
8.20 8.40 8.60 ns
9.88 10.08 10.28 ns
2.5
ns
0
ns
3.8
6.3 ns
2.8
7.1 ns
110 150 ps
210 230 ps
350 370 ps
10 ms
100 ns
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of +/−3ns applied to the input clock signal while data inputs are switching (See Figures 15 and 16). A jitter event of 3ns, represents worse case
jump in the clock edge from most graphics controller VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern (Note 7)
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