DS90C385 Datasheet, PDF (3/17 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) L

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
Worst Case
DS90C365
R_L = 100Ω,
C_L = 5 pF,
Worst Case Pattern
(Figures 1, 4 )
f = 32.5 MHz
f = 40 MHz
f = 65 MHz
f = 85 MHz
ICCTG
Transmitter Supply Current
16 Grayscale
DS90C365
R_L = 100Ω,
C_L = 5 pF,
16 Grayscale Pattern
(Figures 3, 4 )
f = 32.5 MHz
f = 40 MHz
f = 65 MHz
f = 85 MHz
ICCTZ
Transmitter Supply Current
Power Down
Power Down = Low
Driver Outputs in TRI-STATE under
Power Down Mode
Min Typ Max Units
28
42
mA
29
47
mA
34
52
mA
39
57
mA
26
35
mA
27
37
mA
32
42
mA
36
47
mA
10
55
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_OD and ∆V_OD).
Note 4: V_OS previously referred as V_CM.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TCIT
TxCLK IN Transition Time (Figure 6)
TCIP
TxCLK IN Period (Figure 7)
TCIH
TxCLK IN High Time (Figure 7)
TCIL
TxCLK IN Low Time (Figure 7)
TXIT
TxIN Transition Time
Min
1.0
11.76
0.35T
0.35T
1.5
Typ
T
0.5T
0.5T
Max Units
6.0 ns
50 ns
0.65T ns
0.65T ns
6.0 ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
LLHT
LVDS Low-to-High Transition Time (Figure 5)
LHLT
LVDS High-to-Low Transition Time (Figure 5)
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figures 13, 14)
(Note 5)
f = 40 MHz
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figures 13, 14)
(Note 5)
f = 65 MHz
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
Min Typ
0.75
0.75
−0.25 0
Max Units
1.5 ns
1.5 ns
0.25 ns
3.32 3.57 3.82 ns
6.89 7.14 7.39 ns
10.46 10.71 10.96 ns
14.04 14.29 14.54 ns
17.61 17.86 18.11 ns
21.18 21.43 21.68 ns
−0.20 0 0.20 ns
2.00 2.20 2.40 ns
4.20 4.40 4.60 ns
6.39 6.59 6.79 ns
8.59 8.79 8.99 ns
10.79 10.99 11.19 ns
12.99 13.19 13.39 ns
3
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