ADC08D1020_09 Datasheet, PDF (4/44 Pages) National Semiconductor (TI) – Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
3
OutV / SCLK
29
PDQ
4
OutEdge / DDR /
SDATA
15
DCLK_RST /
DCLK_RST+
26
PD
30
CAL
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude
and reduced power consumption. See 1.1.6 The LVDS
Outputs. When the extended control mode is enabled, this
pin functions as the SCLK input which clocks in the serial
data. See 1.2 NORMAL/EXTENDED CONTROL for details
on the extended control mode. See 1.3 THE SERIAL
INTERFACE for description of the serial interface.
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode.
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. (See 1.1.5.2 OutEdge and
Demultiplex Control Setting). When this pin is floating or
connected to 1/2 the supply voltage, DDR clocking is
enabled. When the extended control mode is enabled, this
pin functions as the SDATA input. See 1.2 NORMAL/
EXTENDED CONTROL for details on the extended control
mode. See 1.3 THE SERIAL INTERFACE for description of
the serial interface.
DCLK Reset. When single-ended DCLK_RST is selected by
floating or setting pin 52 logic high, a positive pulse on this
pin is used to reset and synchronize the DCLK outputs of
multiple converters. See 1.5 MULTIPLE ADC
SYNCHRONIZATION for detailed description. When
differential DCLK_RST is selected by setting pin 52 logic low,
this pin receives the positive polarity of a differential pulse
signal used to reset and synchronize the DCLK outputs of
multiple converters.
A logic high on the PDQ pin puts only the "Q" ADC into the
Power Down mode.
Calibration Cycle Initiate. A minimum 1280 input clock cycles
logic low followed by a minimum of 1280 input clock cycles
high on this pin initiates the calibration sequence. See 2.4.2
Calibration for an overview of calibration and 2.4.2.2 On-
Command Calibration for a description of on-command
calibration.
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