ADC08D1020_09 Datasheet, PDF (32/44 Pages) National Semiconductor (TI) – Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

I-Channel Offset
Addr: 2h (0010b)
Write only (0x007F)
D15 D14 D13 D12 D11 D10 D9 D8
(MSB)
Offset Value
(LSB)
D7 D6 D5 D4 D3 D2 D1 D0
Sign 1 1 1 1 1 1 1
Bits 15:8
Bit 7
Bits 6:0
Offset Value. The input offset of the I-
Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides 0.176 mV of offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset, resulting in total offset
adjustment of ±45 mV.
POR State: 0b
Must be set to 1b
I-Channel Full-Scale Voltage Adjust
Addr: 3h (0011b)
Write only (0x807F)
D15 D14 D13 D12 D11 D10 D9 D8
(MSB)
Adjust Value
D7 D6 D5 D4 D3 D2 D1 D0
(LSB) 1 1 1 1 1 1 1
Bits 15:7
Bits 6:0
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of the
nominal 700 mV_P-P differential value.
0000 0000 0
560 mV_P-P
1000 0000 0
Default Value
700 mV_P-P
1111 1111 1
840 mV_P-P
For best performance, it is recommended that the
value in this field be limited to the range of 0110
0000 0b to 1110 0000 0b. i.e., limit the amount of
adjustment to ±15%. The remaining ±5%
headroom allows for the ADC's own full scale
variation. A gain adjustment does not require ADC
re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
Extended Configuration Register
Addr: 9h (1001b)
Write only (0x03FF)
D15 D14 D13 D12 D11 D10 D9 D8
TPO RTD DES IS 0 DLF 1 1
D7 D6 D5 D4 D3 D2 D1 D0
11111111
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bits 9:0
TPO: Test Pattern Output. When this bit is set
1b, the ADC is disengaged and a test pattern
generator is connected to the outputs
including OR. This test pattern will work with
the device in the SDR, DDR and the non-
demultiplex output modes.
POR State: 0b
RTD: Resistor Trim Disable. When this bit is
set to 1b, the input termination resistor is not
trimmed during the calibration cycle and the
DCLK output remains enabled. Note that the
ADC is calibrated regardless of this setting.
POR State: 0b
DES: DES Enable. Setting this bit to 1b
enables the Dual Edge Sampling mode. In
this mode the ADCs in this device are used
to sample and convert the same analog input
in a time-interleaved manner, accomplishing
a sample rate of twice the input clock rate.
When this bit is set to 0b, the device operates
in the normal dual channel mode.
POR State: 0b
IS: Input Select. When this bit is set to 0b the
"I" input is operated upon by both ADCs.
When this bit is set to 1b the "Q" input is
operated on by both ADCs.
POR State: 0b
Must be set to 0b
DLF: Low Frequency. When this bit is set 1b,
the dynamic performance of the device is
improved when the input clock is less than
900MHz.
POR State: 0b
Must be set to 1b
Q-Channel Offset
Addr: Ah (1010b)
Write only (0x007F)
D15 D14 D13 D12 D11 D10 D9 D8
(MSB)
Offset Value
(LSB)
D7 D6 D5 D4 D3 D2 D1 D0
Sign 1 1 1 1 1 1 1
Bits 15:8
Bit 7
Bits 6:0
Offset Value. The input offset of the Q-
Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides about 0.176 mV of
offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
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