ADC08D1020_09 Datasheet, PDF (34/44 Pages) National Semiconductor (TI) – Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

mum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. The du-
ration of the DCLK_RST pulse affects the length of time that
the digital output will take before providing valid data again
after the end of the reset condition. Therefore, the DCLK_RST
pulse width should be made reasonably short within the sys-
tem application constraints. These timing specifications are
listed as t_RH, t_RS, and t_PWR in the Converter Electrical Char-
acteristics.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 7, Figure 8 and Figure 9 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, there are three or four CLK cycles of sys-
tematic delay and the next CLK falling edge synchronizes the
DCLK output with those of other ADC08D1020s in the sys-
tem. The DCLK output is enabled again after a constant delay
(relative to the input clock frequency) which is equal to the
CLK input to DCLK output delay (t_OD). The device always ex-
hibits this delay characteristic in normal operation. The user
has the option of using a single-ended DCLK_RST signal, but
a differential DCLK_RST is strongly recommended due to its
superior timing specifications.
As shown in Figure 7, Figure 8, and Figure 9 of the Timing
Diagrams, there is a delay from the deassertion of
DCLK_RST to the reappearance of DCLK, which is equal to
several cycles of CLK plus t_OD. Note that the deassertion of
DCLK_RST is not latched in until the next falling edge of CLK.
For 1:2 Demux DDR 0° Mode, there are four CLK cycles of
delay; for all other modes, there are three CLK cycles of delay.
If the device is not programmed to allow DCLK to run contin-
uously, DCLK will become inactive during a calibration cycle.
Therefore, it is strongly recommended that DCLK only be
used as a data capture clock and not as a system clock.
The DCLK_RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
1.6 ADC TEST PATTERN
To aid in system debug, the ADC08D1020 has the capability
of providing a test pattern at the four output ports completely
independent of the input signal. The ADC is disengaged and
a test pattern generator is connected to the outputs including
OR. The test pattern output is the same in DES mode and
non-DES mode. Each port is given a unique 8-bit word, alter-
nating between 1's and 0's as described in Table 6 and Table
7.
TABLE 6. Test Pattern by Output Port in
1:2 Demultiplex Mode
Time Qd Id
Q
I OR Comments
T0 01h 02h 03h 04h 0
T1 FEh FDh FCh FBh 1
Pattern
T2 01h 02h 03h 04h 0 Sequence
T3 FEh FDh FCh FBh 1
n
T4 01h 02h 03h 04h 0
Time Qd Id
Q
I OR Comments
T5 01h 02h 03h 04h 0
T6 FEh FDh FCh FBh 1
Pattern
T7 01h 02h 03h 04h 0 Sequence
T8 FEh FDh FCh FBh 1
n+1
T9 01h 02h 03h 04h 0
T10 01h 02h 03h 04h 0
Pattern
T11 ...
...
... ... ... ^{Sequence n}
+2
With the part programmed into the non-demultiplex mode, the
test pattern’s order will be as described in Table 7.
TABLE 7. Test Pattern by Output Port in
Non-demultiplex Mode
Time
Q
I
OR
Comments
T0
01h
02h
0
T1
FEh FDh
1
T2
01h
02h
0
T3
01h
02h
0
T4
FEh FDh
1
T5
FEh FDh
1
T6
01h
02h
0
Pattern
Sequence
n
T7
01h
02h
0
T8
FEh FDh
1
T9
01h
02h
0
T10
01h
02h
0
T11
FEh FDh
1
T12
01h
02h
0
T13
01h
02h
0
T14
FEh FDh
1
Pattern
Sequence
n+1
T15
...
...
...
It is possible for the I and the Q channels' test patterns to be
not synchronized. Either I and Id or Q and Qd patterns may
be slipped by one DCLK.
To ensure that the test pattern starts synchronously in each
port, set DCLK_RST while writing the Test Pattern Output bit
in the Extended Configuration Register. The pattern appears
at the data output ports when DCLK_RST is cleared low. The
test pattern will work at speed and will work with the device in
the SDR, DDR and the non-demultiplex output modes.
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