COP8ACC5 Datasheet, PDF(32/41 Page) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D

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COP8ACC5 Datasheet, PDF (32/41 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D

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Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

S/ADD REG

0000 to 006F

0070 to 007F

xx80 to xxAF

xxB0

XXB1

xxB2

xxB3

xxB4

xxB5

xxB6

xxB7

xxB8 to xxBF

xxC0

xxC1

xxC2

xxC3

xxC4

xxC5

xxC6

xxC7

xxC8

xxC9

xxCA

xxCB

xxCC

xxCD

xxCE

xxCF

xxD0

xxD1

xxD2

xxD3

xxD4

xxD5

xxD6

xxD7

xxD8

Contents

On-Chip RAM bytes (112

bytes)

Unused RAM Address Space

(Reads As All Ones)

Unused RAM Address Space

(Reads Undefined Data)

Reserved

Comparator Select Register

(CMPSL)

Reserved

WATCHDOG Service Register

(Reg:WDSVR)

MIWU Edge Select Register

(Reg:WKEDG)

MIWU Enable Register

(Reg:WKEN)

MIWU Pending Register

(Reg:WKPND)

Reserved

CAPTLO (Capture Timer

Low-Byte)

CAPTHI (Capture Timer

High-Byte)

CAPCNTL (Capture Timer

Control Register)

Idle Timer Control Register

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Reserved

Address

S/ADD REG

Contents

xxD9

Reserved

xxDA

Reserved

xxDB

Reserved

xxDC

Port D

xxDD to DF

Reserved

xxE0 to xxE5

Reserved

xxE6

Timer T1 Autoload Register

T1RB Lower Byte

xxE7

Timer T1 Autoload Register

T1RB Upper Byte

xxE8

ICNTRL Register

xxE9

MICROWIRE/PLUS Shift

xxEA

Timer T1 Lower Byte

xxEB

Timer T1 Upper Byte

xxEC

Timer T1 Autoload Register

T1RA Lower Byte

xxED

Timer T1 Autoload Register

T1RA Upper Byte

xxEE

CNTRL Control Register

xxEF

PSW Register

xxF0 to xxFB

On-Chip RAM Mapped as

Registers

xxFC

X Register

xxFD

SP Register

xxFE

B Register

xxFF

Reserved

0100-017F

Reserved

Reading memory locations 0070H-007FH (Segment 0) will

return all ones. Reading unused memory locations

0080H-00AFH (Segment 0) will return undefined data. Read-

ing memory locations from other Segments (i.e., Segment 2,

Segment 3,â¦etc.) will return undefined data.

Addressing Modes

There are ten addressing modes, six for operand addressing

and four for transfer of control.

OPERAND ADDRESSING MODES

This is the ânormalâ addressing mode. The operand is the

data memory addressed by the B pointer or X pointer.

ment of pointer)

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

pointer or X pointer. This is a register indirect mode that au-

tomatically post increments or decrements the B or X regis-

ter after executing the instruction.

Direct

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

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