COP8ACC5 Datasheet, PDF (14/41 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D

Timers
The device contains a very versatile set of timers (T0 and
T1). All timers and associated autoreload/capture registers
power up containing random data.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, t_C. The user cannot read or
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
Figure 8 is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
Bits 11 through 15 of the ITMR register can be selected for
triggering the IDLE Timer interrupt. Each time the selected
bit underflows (every 4k, 8k, 16k, 32k or 64k instruction
cycles), the IDLE Timer interrupt pending bit T0PND is set,
thus generating an interrupt (if enabled), and bit 6 of the Port
G data register is reset, thus causing an exit from the IDLE
mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer in-
terrupt enable bit T0EN must be set, and the GIE (Global In-
terrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
tively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to the Power Save
Modes section.
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bits 3–7 of the ITMR Register are reserved and
should not be used as software flags.
ITMR Register (Address X’0xCF)
Bit 7
Reserved
Bit 3
ITSEL2
ITSEL1
ITSEL0
Bit 0
TABLE 3. Idle Timer Window Length
ITSEL2 ITSEL1 ITSEL0
Idle Timer Period
(Instruction Cycles)
0
0
0
4,096
0
0
1
8,192
0
1
0
16,384
0
1
1
32,768
1
X
X
65,536
The ITMR register is cleared on Reset and the Idle Timer pe-
riod is reset to 4,096 instruction cycles.
Any time the IDLE Timer period is changed there is the pos-
sibility of generating a spurious IDLE Timer interrupt by set-
ting the T0PND bit. The user is advised to disable IDLE
Timer interrupts prior to changing the value of the ITSEL bits
of the ITMR Register and then clear the T0PND bit before at-
tempting to synchronize operation to the IDLE Timer.
DS012865-9
FIGURE 8. Functional Block Diagram for Idle Timer T0
TIMER T1
The device has a powerful timer/counter block. The timer
consists of a 16-bit timer, T1, and two supporting 16-bit
autoreload/capture registers, R1A and R1B. The timer block
has two pins associated with it, T1A and T1B. The pin T1A
supports I/O required by the timer block, while the pin T1B is
an input to the timer block. The powerful and flexible timer
block allows the device to easily perform all timer functions
with minimal software overhead. The timer block has three
operating modes: Processor Independent PWM mode, Ex-
ternal Event Counter mode, and Input Capture mode.
The control bits T1C3, T1C2, and T1C1 allow selection of the
different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to gen-
erate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
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