COP8ACC5 Datasheet, PDF(20/41 Page) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D

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COP8ACC5 Datasheet, PDF (20/41 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D

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Analog Function Block

This device contains an analog function block with the intent

to provide a function which allows for single slope, low cost,

A/D conversion of up to 6 channels.

CMPSL REGISTER (ADDRESS Xâ00B7)

CMPT2B CMPISEL2 CMPISEL1 CMPISEL0 CMPOE CSEN CMPEN CMPNEG

Bit 7

Bit 0

The CMPSL register contains the following bits:

CMPT2B

Selects the âHigh Speed 16-bit Capture

Timerâ input to be driven directly by the

comparator output. If the comparator is dis-

abled (CMPEN=0), this function is dis-

abled, i.e. the Capture Timer input is con-

nected to GND.

CMPISEL0/1/2 Will select one of seven possible sources

(I0/I2/I3/I4/I5/I6/internal reference) as a

positive input to the comparator (see Table

4 for more information)

CMPOE

Enables the comparator output to either pin

I3 or pin I7 (â1â=enable) depending on the

value of CMPISEL0/1/2.

CSEN

Enables the internal constant current

source. This current source provides a

nominal 20 ÂµA constant current at the I1

pin. This current can be used to ensure a

linear charging rate on an external capaci-

tor. This bit has no affect and the current

source is disabled if the comparator is not

enabled (CMPEN=0).

CMPEN

Enable the comparator (â1â = enable)

CMPNEG

Will drive I1 to a low level. This bit can be

used to discharge an external capacitor.

This bit is disabled if the comparator is not

enabled (CMPEN=0).

The Comparator Select Register is cleared on RESET (the

comparator is disabled). To save power the program should

also disable the comparator before the ÂµC enters the HALT/

IDLE modes. Disabling the comparator will turn off the con-

stant current source and the VCC/2 reference, disconnect the

comparator output from the Capture Timer input and pin I3/I7

and remove the low on I1 caused by CMPNEG.

It is often useful for the userâs program to read the result of

a comparator operation. Since I1 is always selected to be

COMPIN â when the comparator is enabled (CMPEN=1),

the comparator output can be read internally by reading bit 1

(CMPRD) of register PORTI (RAM address 0xD7).

The following table lists the comparator inputs and outputs

versus the value of the CMPISEL0/1/2 bits. The output will

only be driven if the CMPOE bit is set to 1.

FIGURE 13. Analog Function Block

DS012865-14

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