LP3928 Datasheet, PDF (3/11 Pages) National Semiconductor (TI) – High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator

Package Outline and Connection Diagrams
20039103
Bottom View
16 Bump micro SMD Package
See NSC Package Number TLA16AAA
20039104
Note: The actual physical placement of the package marking will vary from
part to part. The package marking “XY” will designate the date code, “TT” is
a NSC internal code for die traceability. Both will vary considerably. L8B
identifies the device.
Top View
Pin Description
Pin Name
A1
A2
A3
B1
B2
B3
DIR1
DIR2
DIR3
V_CCA
V_CCB
V_BAT
GND
EN1
EN2
LatchClk
micro SMD
Bump Identifier
C4
D4
D3
C1
D1
D2
B3
B2
C3
B4
B1
A1
A3
A4
A2
C2
Logic Level
1.8V
1.8V
1.8V
2.85V
2.85V
2.85V
1.8V
1.8V
1.8V
1.8V
1.8V
2.85V
Function
1.8V I/O Channel, (Note 1)
1.8V I/O Channel, (Note 1)
1.8V I/O Channel, (Note 1)
2.85V I/O Channel, (Note 1)
2.85V I/O Channel, (Note 1)
2.85V I/O Channel, (Note 1)
Direction control input Channel 1: ‘1’: A→B; 0; B→A
Direction control input Channel 2: ‘1’: A→B; 0; B→A
Direction control input Channel 3: ‘1’: A→B; 0; B→A
IC supply to the 1.8V side
IC supply, 2.85V output from LDO
LDO supply, Battery voltage
Power ground connection
Mode pin 1, see Table 1 for modes and settings
Mode pin 2, see Table 1 for modes and settings
Clock input: rising edge latches B inputs (DIR=0, normal mode)
Note 1: Pin pairs A1–B1, A2–B2 and A3–B3 form 3 independent bi-directional level-shifting channels.
Inputs
EN1
EN2
0
0
0
1
1
0
1
1
TABLE 1. Operation Modes
State
Level shifter off: High Z state on A₁–A₃, B₁–B₃, LDO off
Level shifter off: High Z state on A₁–A₃, B₁–B₃, LDO on
Latch bypassed in B to A direction, LDO=on (Note 2)
ON, normal mode (latch active)
Note 2: LatchClk is not used here. It should not be left floating.
3
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