DS91C180_07 Datasheet, PDF (3/14 Pages) National Semiconductor (TI) – 100 MHz M-LVDS Line Driver/Receiver Pair

Absolute Maximum Ratings (Note 1)
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Supply Voltage, V_CC
Control Input Voltages
Driver Input Voltage
Driver Output Voltages
−0.3V to +4V
−0.3V to (V_CC + 0.3V)
−0.3V to (V_CC + 0.3V)
−1.8V to +4.1V
Receiver Input Voltages
−1.8V to +4.1V
Receiver Output Voltage
−0.3V to (V_CC + 0.3V)
Maximum Package Power Dissipation at +25°C
SOIC Package
1.1 W
Derate SOIC Package
8.8 mW/°C above +25°C
Thermal Resistance
 θ_JA
113.7 °C/W
 θ_JC
Maximum Junction Temperature
36.9 °C/W
150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
260°C
ESD Ratings:
(HBM 1.5kΩ, 100pF)
(EIAJ 0Ω, 200pF)
(CDM 0Ω, 0pF)
≥ 5 kV
≥ 250 V
≥ 1000 V
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage, V_CC
Voltage at Any Bus Terminal
3.0 3.3 3.6 V
−1.4
+3.8 V
 (Separate or Common-Mode)
Differential Input Voltage V_ID
High Level Input Voltage V_IH
2.0
Low Level Input Voltage V_IL
0
Operating Free Air
2.4 V
V_CC V
0.8 V
Temperature T_A
−40 +25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8)
Symbol
Parameter
Conditions
Min Typ
M-LVDS Driver
|V_YZ|
ΔV_YZ
Differential output voltage magnitude
Change in differential output voltage magnitude
between logic states
R_L = 50Ω, C_L = 5pF
Figure 2 and Figure 4
480
−50 0
V_OS(SS)
|ΔV_OS(SS)|
Steady-state common-mode output voltage
Change in steady-state common-mode output
voltage between logic states
R_L = 50Ω, C_L = 5pF
Figure 2 and Figure 3
0.3 1.8
0
V_OS(PP)
V_Y(OC)
V_Z(OC)
V_P(H)
V_P(L)
Peak-to-peak common-mode output voltage
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
I_IH
High-level input current (LVTTL inputs)
I_IL
Low-level input current (LVTTL inputs)
V_IKL
Input Clamp Voltage (LVTTL inputs)
I_OS
Differential short-circuit output current
M-LVDS Receiver
(V_OS(pp) @ 500KHz clock)
Figure 5
R_L = 50Ω, C_L = 5pF,
C_D = 0.5pF
Figure 7 and Figure 8 (Note 9)
V_IH = 2.0V
V_IL = 0.8V
I_IN = -18 mA
Figure 6
143
0
0
−0.2V_S
S
-15
-15
-1.5
-43
V_IT+
Positive-going differential input voltage threshold See Function Tables
Type 1
20
Type 2
94
V_IT−
Negative-going differential input voltage threshold See Function Tables
Type 1 −50 20
Type 2 50 94
V_OH
High-level output voltage
I_OH = −8mA
V_OL
Low-level output voltage
I_OL = 8mA
I_OZ
TRI-STATE output current
V_O = 0V or 3.6V
I_OSR
Short circuit Rrceiver output current (LVTTL Output) V_O = 0V
2.4 2.7
0.28
−10
-90 -48
Max Units
650 mV
+50 mV
2.1
V
+50 mV
mV
2.4
V
2.4
V
1.2V_SS V
V
15
μA
15
μA
V
43 mA
50 mV
150 mV
mV
mV
V
0.4
V
10
μA
mA
3
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