THS4211 Datasheet, PDF (27/50 Pages) Texas Instruments – LOW-DISTORTION HIGH-SPEED VOLTAGE FEEDBACK AMPLIFIER

THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4211. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good
high frequency performance. Again, keep their
leads and PCB trace length as short as possible.
Never use wire-wound type resistors in a
high-frequency application. Since the output pin
and inverting input pin are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistor, if any, as
close as possible to the output pin. Other network
components,
such
as
noninverting
input-termination resistors, should also be placed
close to the package. Where double-side
component mounting is allowed, place the
feedback resistor directly under the package on
the other side of the board between the output
and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors,
excessively high resistor values can create
significant time constants that can degrade
performance. Good axial metal-film or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values >
2.0 kΩ, this parasitic capacitance can add a pole
and/or a zero below 400 MHz that can effect
circuit operation. Keep resistor values as low as
possible, consistent with load driving
considerations. A good starting point for design is
to set the R_f to 249 Ω for low-gain, noninverting
applications. This setting automatically keeps the
resistor noise terms low and minimizes the effect
of their parasitic capacitance.
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set R_ISO from the
plot of recommended R_ISO vs capacitive load
(See Figure 88). Low parasitic capacitive loads (<
4 pF) may not need an R_(ISO), since the THS4211
is nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an R_(ISO) are allowed as the signal gain
increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB
signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline
layout techniques). A 50-Ω environment is
normally not necessary onboard, and in fact a
higher impedance environment improves
distortion as shown in the distortion versus load
plots. With a characteristic board trace
impedance defined on the basis of board material
and trace dimensions, a matching series resistor
into the trace from the output of the THS4211 is
used as well as a terminating shunt resistor at the
input of the destination device. Remember also
that the terminating impedance is the parallel
combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the
trace impedance. If the 6-dB attenuation of a
doubly-terminated transmission line is
unacceptable, a long trace can be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case and set
the series resistor value as shown in the plot of
R_(ISO) vs capacitive load (See Figure 88). This
setting does not preserve signal integrity or a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
5. Socketing a high speed part like the THS4211
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create a troublesome parasitic
network which can make it almost impossible to
achieve a smooth, stable frequency response.
Best results are obtained by soldering the
THS4211 onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS4211 and THS4215 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 89(a) and Figure 89(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 89(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad.
The PowerPAD package allows both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also
be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
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Product Folder Link(s): THS4211 THS4215
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