THS4211 Datasheet, PDF (26/50 Pages) Texas Instruments – LOW-DISTORTION HIGH-SPEED VOLTAGE FEEDBACK AMPLIFIER

THS4211
THS4215
SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com
Dividing this expression by the noise gain [NG= (1 +
R_f/R_g) ] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 5:
Ǹ ǒ Ǔ _{EO +}
2
E_NI2 ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S )
I_BIR_f
NG
)
4kTR
NG
f
(5)
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
A high-speed, high open-loop gain amplifier like the
THS4211 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier's open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. When the primary considerations
are frequency response flatness, pulse response
fidelity, or distortion, the simplest and most effective
solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a
higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4211. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4211 output pin (see Board Layout
Guidelines).
The criterion for setting this R_(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load. For a gain of +2, the frequency response at the
output pin is already slightly peaked without the
capacitive load, requiring relatively high values of
R_(ISO) to flatten the response at the load. Increasing
the noise gain also reduces the peaking.
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
1
R_(ISO) = 10 Ω
0.5
C_L = 100 pF
V_S =±5 V
0
-0.5
-1
-1.5
-2
R_(ISO) = 15 Ω
C_L = 50 pF
R_(ISO) = 25 Ω
C_L = 10 pF
-2.5
-3
100 k
1M
10 M
100 M
1G
Capacitive Load - Hz
Figure 88. Isolation Resistor Diagram
BOARD LAYOUT
Achieving optimum performance with a high
frequency amplifier like the THS4211 requires careful
attention to board layout parasitics and external
component types.
Recommendations that optimize performance include
the following:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional band limiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on
the board.
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors,
effective at lower frequency, should also be used
on the main supply pins. These may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the PCB.
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