LP3918 Datasheet, PDF (25/30 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

No-Load Stability
The LDO's on the LP3918 will remain stable in regulation with
no external load.
TABLE 20. LDO Output Capacitors Recommended Specification
Symbol
C_o(LDO1)
C_o(LDO2)
C_o(LDO3)
C_o(LDO4)
C_o(LDO5)
C_o(LDO6)
C_o(LDO7)
Parameter
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitor Type
X5R. X74
X5R. X74
X5R. X74
X5R. X74
X5R. X74
X5R. X74
X5R. X74
Limit
Typ
Min
Max
1.0
0.7
2.2
1.0
0.7
2.2
1.0
0.7
2.2
1.0
0.7
2.2
1.0
0.7
2.2
1.0
0.7
2.2
1.0
0.7
2.2
Units
µF
µF
µF
µF
µF
µF
µF
Note: The capacitor tolerance should be 30% or better over
the full temperature range. X7R or X5R capacitors should be
used. These specifications are given to ensure that the ca-
pacitance remains within these values over all conditions
within the application. See Capacitor Characteristics section
in Application Information.
Thermal Shutdown
The LP3918 has internal limiting for high on-chip tempera-
tures caused by high power dissipation etc. This Thermal
Shutdown, TSD, function monitors the temperature with re-
spect to a threshold and results in a device power-down.
If the threshold of +160°C has been exceeded then the device
will power down. Recovery from this TSD event can only be
initiated after the chip has cooled below +115°C. This device
recovery is controlled by the APU_TSD_EN bit (bit 1) in con-
trol register MISC, 8h'1C. See Table 22 If the APU_TSD_EN
is set low then the device will shutdown requiring a new start
up event initiated by PWR_ON, HF_PWR, or CHG_IN. If
APU_TSD_EN is set high then the device will power up au-
tomatically when the shutdown condition clears. In this case
the control register settings are preserved for the device
restart.
The threshold temperature for the device to clear this TSD
event is 115°C. This threshold applies for any start up thus
the device temperature must be below this threshold to allow
a start up event to initiate power up.
Further Register Information
STATUS REGISTER READ ONLY
TABLE 21. Register Address 8h'0C: Status
BIT
NAME
FUNCTION (if bit = '1')
7
PWR_ON PMU start up is initiated by
_TRIG
PWR_ON.
6
HF_PWR PMU start up is initiated by
_TRIG
HF_PWR.
5
CHG_IN PMU start up is initiated by
_TRIG
CHG_IN.
Bits <4..0> are not used.
MISC CONTROL REGISTER
TABLE 22. Register Address 8h'1C: Misc
BIT
NAME
FUNCTION (if bit = '1')
1
APU_TSD 1b' 0: Device will shutdown
_EN
completely if thermal shutdown
occurs. Requires a new start up
event to restart the PMU.
1b'1: Device will start up
automatically after thermal
shutdown condition is removed.
(Device tries to keep its internal
state.)
0 PWR_HOLD 1b'0: If PWR_HOLD is low for 35ms
DELAY the device will shutdown. (Default)
1b'1: If PWR_HOLD is low for
350ms the device will shutdown.
Bits <7..2> are not used.
I²C Compatible Serial Bus Interface
INTERFACE BUS OVERVIEW
The I²C compatible synchronous serial interface provides ac-
cess to the programmable functions and registers on the
device.
This protocol uses a two-wire interface for bi-directional com-
munications between the IC’s connected to the bus. The two
interface lines are the Serial Data Line (SDA), and the Serial
Clock Line (SCL). These lines should be connected to a pos-
itive supply, via a pull-up resistor of 1.5KΩ, and remain HIGH
even when the bus is idle.
Every device on the bus is assigned a unique address and
acts as either a Master or a Slave depending on whether it
generates or receives the serial clock (SCL).
DATA TRANSACTIONS
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (SCL). Con-
sequently, throughout the clock’s high period, the data should
remain stable. Any changes on the SDA line during the high
state of the SCL and in the middle of a transaction, aborts the
current transaction. New data should be sent during the low
SCL state. This protocol permits a single data line to transfer
both command/control information and data using the syn-
chronous serial clock.
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