LP3918 Datasheet, PDF (12/30 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

Register Information, Slave Address Code 7h’7E
TABLE 3. Control Registers
Addr ^Register
(default value)
8h'00
OP_EN
(0000 0101)
8h'01
LDO1PGM O/P
(0000 0001)
8h'02 ^{LDO2PGM O/P}
(0000 1011)
8h'03 ^{LDO3PGM O/P}
(0000 1011)
8h'04 ^{LDO4PGM O/P}
(0000 1011)
8h'05
LDO5PGM O/P
(0000 1011)
8h'06
LDO6PGM O/P
(0000 1011)
8h'07 ^{LDO7PGM O/P}
(0000 1011)
8h'0C ^STATUS
(0000 0000)
CHGCNTL1
8h'10
(0000 1001)
8h'11
CHGCNTL2
(0000 0001)
8h'12
CHGCNTL3
(0001 0010)
8h'13 CHGSTATUS1
8h'14 CHGSTATUS2
8h'1C MISC Control1
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
LDO7_EN LDO3_EN
X
LDO1_EN
X
X
X
X
V1_OP[3] V1_OP[2] V1_OP[1] V1_OP[0]
X
X
X
X
V2_OP[3] V2_OP[2] V2_OP[1] V2_OP[0]
X
X
X
X
V3_OP[3] V3_OP[2] V3_OP[1] V3_OP[0]
X
X
X
X
V4_OP[3] V4_OP[2] V4_OP[1] V4_OP[0]
X
X
X
X
V5_OP[3] V5_OP[2] V5_OP[1] V5_OP[0]
X
X
X
X
V6_OP[3] V6_OP[2] V6_OP[1] V6_OP[0]
X
X
X
X
V7_OP[3] V7_OP[2] V7_OP[1] V7_OP[0]
PWR_ON HF_PWR
_TRIG
_TRIG
CHG_IN
_TRIG
USBMODE CHGMODE
_EN
_EN
Force EOC
X
TOUT_
doubling
Prog_
ICHG[4]
VTERM[1] VTERM[0]
Batt_Over
_Out
CHGIN_
OK_Out
EOC
Tout_
Fullrate
X
EN_Tout
Prog_
ICHG[3]
Prog_
EOC[1]
Tout_
Prechg
X
X
X
En_EOC
X
EN_CHG
Prog_
ICHG[2]
Prog_
EOC[0]
Prog_
ICHG[1]
Prog_
VRSTRT[1]
Prog_
ICHG[0]
Prog_
VRSTRT[0]
LDO Mode Fullrate
PRECHG
Tout_
ConstV
APU_TSD_EN
Bad_Batt
PS_HOLD
_DELAY
X
(R/O)
Not Used
Bits are Read Only type.
Codes other than those shown in the table are disallowed.
Note that for Serial Interface operation and thus register control, LDO2 must be active to provide the power for the internal logic.
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