LP3918 Datasheet, PDF (23/30 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

IMON CHARGE CURRENT MONITOR
Charge current is monitored within the charger section and a
proportional voltage representation of the charge current is
presented at the IMON output pin. The output voltage rela-
tionship to the actual charge current is represented in the
following graph and by the equation:
V_IMON(mV) = (2.47 x I_CHG)(mA)
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FIGURE 4. IMON Voltage vs Charge Current
Note that this function is not available if there is no input at
CHG_IN or if the charger is off due to the input at CHG_IN
being outwith the operating voltage range.
LDO Information
OPERATIONAL INFORMATION
The LP3918 has 7 LDO's of which 3 are enabled by default,
LDO's 1,2 and 3 are powered up during the power up se-
quence. LDO4, 5 and 6 are separately, externally enabled
and will follow LDO2 in start up if their respective enable pin
is pulled high. LDO2, LDO3 and LDO7 can be enabled/dis-
abled via the serial interface.
LDO2 must remain in regulation otherwise the device will
power down. While LDO1 is enabled this must also be in reg-
ulation for the device to remain powered. If LDO1 is disabled
via I2C interface the device will not shut down.
INPUT VOLTAGES
There are two input voltage pins used to power the 7LDO's
on the LP3918. V_IN2is the supply for LDO3, LDO4, LDO5,
LDO6 and LDO7. V_IN1is the supply for LDO1 and LDO2.
These input voltages should be tied to the Batt pin in the
application.
PROGRAMMING INFORMATION
Enable via Serial Interface
TABLE 18. Register Address 8h'00: OP_EN
BIT
NAME
FUNCTION
0
LDO1_EN Bit set to '0' - LDO disabled
2
LDO3_EN ^{Bit set to '1' - LDO enabled}
3
LDO7_EN
Note that the default setting for this Register is [0000 0101].
This shows that LDO1 and 3 are enabled by default whereas
LDO7 is not enabled by default on start up.
LDO OUTPUT PROGRAMMING
Regi
ster
Add
(hex)
01
02
03
04
05
06
07
NAME
LDO1PGM
O/P
LDO2PGM
O/P
LDO3PGM
O/P
LDO4PGM
O/P
LDO5PGM
O/P
LDO6PGM
O/P
LDO7PGM
O/P
TABLE 19.
Data Range
(hex)
Output Voltage
03 - 0F
00 - 0F
05 - 0C
00 - 0F
05 - 0C
05 - 0C
00 - 0F
1.5V to 3.3V
(def. 1.8V)
2.5V to 3.3V
(def 3.0V)
2.7V to 3.05V
(def 3.0V)
1.5V to 3.3V
(def 3.0V)
2.7V to 3.05V
(def 3.0V)
2.7V to 3.05V
(def 3.0V)
1.5V to 3.3V
(def 3.0V)
See Table 2 for full programmable range of values.
EXTERNAL CAPACITORS
The Low Drop Out Linear Voltage regulators on the LP3918
require external capacitors to ensure stable outputs. The
LDO's on the LP3918 are specifically designed to use small
surface mount ceramic capacitors which require minimum
board space. These capacitors must be correctly selected for
good performance
INPUT CAPACITOR
Input capacitors are required for correct operation. It is rec-
ommended that a 10µF capacitor be connected between
each of the voltage input pins and ground (this capacitance
value may be increased without limit). This capacitor must be
located a distance of not more than 1cm from the input pin
and returned to a clean analogue ground. A ceramic capacitor
is recommended although a good quality tantalum or film ca-
pacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have surge current rat-
ing sufficent for the application. There are no requirements for
the ESR (Equivalent Series Resistance) on the input capaci-
tor, but tolerance and temparature coefficient must be con-
sidered when selecting the capacitor to ensure the capaci-
tance will remain within its operational range over the entire
operating temperature range and conditions.
Output Capacitor
Correct selection of the output capacitor is critical to ensure
stable operation in the intended application.The output ca-
pacitor must meet all the requirements specified in the rec-
ommended capacitor table over all conditions in the applica-
tion. These conditions include DC-bias, frequency and
temperature. Unstable operation will result if the capacitance
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