LMH0341_09 Datasheet, PDF (22/28 Pages) National Semiconductor (TI) – 3 Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface

ADD 'h Name
2B
Event
Configuration
2C
Reserved
2D
Error Monitor
2E
Error Threshold
2F
Error Threshold
30–3A Reserved
3B
Data Rate
Bits Field
R/W Default Description
Allows control over the counting of error events on the clock recovery PLL
7:4 Reserved
3
Event Count
r/w
0
0: Select CDR Event counter for reading — events
Select
are counted for a loss of the RXCLK signal, or a loss
of lock
1: Select data event counter
2
Reset CDR
r/w
Error Count
0
Resets CDR Event count
1
Reset Link
r/w
Error Count
0
resets data event counter
0
enable count
r/w
0
enables event counters
Controls Error Monitoring functions
7:5 Reserved
4
Accumulate
r/w
0
Error Count
3
8b10b error
r/w
0
disable
2
clear event
r/w
0
count
1
select error
r/w
0
count
0
Normal Error
r/w
Disable
Sets the error threshold LSBs
7:0 Error Threshold r/w
0
0x10h
Sets the error threshold MSBs
Error Threshold r/w
00
Enable counting accumulation of errors
When set, disables 8b10b errors from being counted,
or from affecting the status of the LOCKpin
When set, clears the number of errors in both the
current and previous state of the error count
Select which error count to display
0: Number of errors in current run
1: Number of errors within the selected timing window
Disable exiting NORMAL state when the number of
errors exceeds the error threshold
Error threshold above which the device stops
receiving data and transferring it to the RXOUT pins.
Error threshold above which the device stops
receiving data and transferring it to the RXOUT pins.
This Register provides information about the rate at which the receive PLL is locked
7
Reserved
6:4 Freq Range
r
111 001: 270 Mbps
011: 1.485 Gbps
110: 2.97 Gbps
111: Unlocked
3:0 Reserved
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