LMH0341_09 Datasheet, PDF (21/28 Pages) National Semiconductor (TI) – 3 Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface

ADD 'h Name
20
Control
21
DVB_ASI
22
Override
23–26 Reserved
27
LVDS Control 1
28
LVDS Control 2
29–2A Reserved
Bits Field
R/W Default Description
7:3 Reserved
2
Data Order
r/w
0
Determines deserialization order —
0: Expects LSB to be received first
1:Expects MSB to be received first
1
Reset Channel r/w
0
Writing a '1' to this bit forces a reset of the channel
0
Digital
r/w
Powerdown
0
Writing a '1' to this bit will shut down several of the
digital processing sections of the product to save
power.
This register allows the device to be placed in DVB_ASI mode or standard operation mode
7:5 Reserved
4
RX_MUX_SEL r/w
0
If enabled by register 22, then this bit will override the
RX_MUX_SEL pin.
3:2 Reserved
1:0 DVB_ASI
r/w
0
00,01,10: Standard Operation
11: DVB_ASI
This register allows the user to control the DVB_ASI and input select functions via the SMBus interface
rather than the pin controls.
7:5 Reserved
4
RX_MUX
Control
Override
r/w
0
Writing a '1' to this register allows register 21 to control
the state of the input multiplexer — if the bit is set to
'0' then the selection will be determined by the state
of the RX_MUX_SEL pin
3:1 Reserved
0
DVB_ASI
Override
Writing a '1' to this register allows register 21 to control
the state of the DVB_ASI Select pin — if the bit is set
to '0' then the selection will be determined by the state
of the DVB_ASI pin if '1' then the contents of register
21 take precidence
This register allows control of the LVDS output pins — using this register individual LVDS outputs can
be enabled or disabled, and the outputs can be switched to high output mode
7
LVDS_VOD
r/w
0
With a '0' the V_OD of the LVDS output are as described
in the electrical characteristics table, writing a '1' to
this bit generates a larger V_ODallowing longer traces
to be driven, and increasing total power dissipation
6
LVDS Control
r/w
0
Writing a '1' to this bit allows the LVDS outputs to be
controlled via the SMBus
5
RXCLK Enable r/w
0
Enables the RXCLK output driver
4
RX4 Enable
r/w
0
Enables RX4 output driver
3
RX3 Enable
r/w
0
Enables RX3 output driver
2
RX2 Enable
r/w
0
Enables RX2 output driver
1
RX1 Enable
r/w
0
Enables RX1 output driver
0
RX0 Enable
r/w
0
Enables RX0 output driver
More bits allowing control over the LVDS outputs
7
Reserved
6
LVDS Reset
r/w
0
Resets LVDS Block
5
RXCLK Rate
r/w
1
1: RXCLK is a DDR clock
0: RXCLI is at a rate of DDR/2
4
RXCLK Invert
r/w
0
Inverts the polarity of the RXCLK signal
3:2 LVDS Clock
r/w
10'b Each LSB adds 80ps delay to the RXCLK signal path,
delay
allowing the setup and hold times to be adjusted.
1:0 Reserved
21
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