LMH6505 Datasheet, PDF (18/20 Pages) National Semiconductor (TI) – Wideband, Low Power, Linear-in-dB, Variable Gain Amplifier

Application Information (Continued)
FIGURE 10. Automatic Gain Control Circuit #2
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CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION
BOARDS
A good high frequency PCB layout including ground plane
construction and power supply bypassing close to the pack-
age are critical to achieving full performance. The amplifier is
sensitive to stray capacitance to ground at the I^- input (pin 7)
so it is best to keep the node trace area small. Shunt
capacitance across the feedback resistor should not be used
to compensate for this effect. Capacitance to ground should
be minimized by removing the ground plane from under the
body of R_G. Parasitic or load capacitance directly on the
output (pin 6) degrades phase margin leading to frequency
response peaking.
The LMH6505 is fully stable when driving a 100Ω load. With
reduced load (e.g. 1k.) there is a possibility of instability at
very high frequencies beyond 400 MHz especially with a
capacitive load. When the LMH6505 is connected to a light
load as such, it is recommended to add a snubber network to
the output (e.g. 100Ω and 39 pF in series tied between the
LMH6505 output and ground). C_L can also be isolated from
the output by placing a small resistor in series with the output
(pin 6).
Component parasitics also influence high frequency results.
Therefore it is recommended to use metal film resistors such
as RN55D or leadless components such as surface mount
devices. High profile sockets are not recommended.
National Semiconductor suggests the following evaluation
board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
LMH6505
Package
SOIC
Evaluation Board
Part Number
CLC730066
The evaluation board can be shipped when a device sample
request is placed with National Semiconductor. Evaluation
board documentation can be found in the LMH6505 product
folder at www.National.com.
www.national.com
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