LMH6321 Datasheet, PDF (18/21 Pages) National Semiconductor (TI) – 300 mA High Speed Buffer with Adjustable Current Limit

Application Hints (Continued)
20138630
FIGURE 4. Thermal Resistance (typ) for 7-L TO-263
Package Mounted on 1 oz. (0.036 mm) PC Board Foil
20138631
FIGURE 5. Derating Curve for TO-263 package.
No Air Flow
TABLE 1. θ_JA vs. Copper Area and P_D for TO-263. 1.0
oz cu Board. No Air Flow. Ambient Temperature = 24˚C
Copper Area
1 Layer = 1”x2” cu
Bottom
2 Layer = 1”x2” cu
Top & Bottom
2 Layer = 2”x2” cu
Top & Bottom
2 Layer = 2”x4” cu
Top & Bottom
θJA @ 1.0W
(˚C/W)
62.4
36.4
23.5
19.8
θJA @ 2.0W
(˚C/W)
54.7
32.1
22.0
17.2
As seen in the previous example, buffer dissipation in DC
circuit applications is easily computed. However, in AC cir-
cuits, signal wave shapes and the nature of the load (reac-
tive, non-reactive) determine dissipation. Peak dissipation
can be several times the average with reactive loads. It is
particularly important to determine dissipation when driving
large load capacitance.
A selection of thermal data for the PSOP package is shown
in Table 2. The table summarized θ_JA for both 0.5 watts and
0.75 watts. Note that the thermal resistance, for both the
TO-263 and the PSOP package is lower for the higher power
dissipation levels. This phenomenon is a result of the prin-
ciple of Newtons Law of Cooling. Restated in term of heat-
sink cooling, this principle says that the rate of cooling and
hence the thermal conduction, is proportional to the tem-
perature difference between the junction and the outside
environment (ambient). This difference increases with in-
creasing power levels, thereby producing higher die tem-
peratures with more rapid cooling.
TABLE 2. θ_JA vs. Copper Area and P_D for PSOP. 1.0 oz
cu Board. No Airflow. Ambient Temperature = 22˚C
Copper Area/Vias
1 Layer = 0.05 sq. in.
(Bottom) + 3 Via
Pads
1 Layer = 0.1 sq. in.
(Bottom) + 3 Via
Pads
1 Layer = 0.25 sq. in.
(Bottom) + 3 Via
Pads
1 Layer = 0.5 sq. in.
(Bottom) + 3 Via
Pads
1 Layer = 1.0 sq. in.
(Bottom) + 3 Via
Pads
2 Layer = 0.5 sq. in.
(Top)/ 0.5 sq. in.
(Bottom) + 33 Via
Pads
2 Layer = 1.0 sq. in.
(Top)/ 1.0 sq. in.
(Bottom) + 53 Via
Pads
θJA @ 0.5W
(˚C/W)
141.4
134.4
115.4
105.4
100.5
93.7
82.7
θJA @ 0.75W
(˚C/W)
138.2
131.2
113.9
104.7
100.2
92.5
82.2
ERROR FLAG OPERATION
The LMH6321 provides an open collector output at the EF
pin that produces a low voltage when the Thermal Shutdown
Protection is engaged, due to a fault condition. Under normal
operation, the Error Flag pin is pulled up to V⁺ by an external
resistor. When a fault occurs, the EF pin drops to a low
voltage and then returns to V⁺ when the fault disappears.
This voltage change can be used as a diagnostic signal to
alert a microprocessor of a system fault condition. If the
function is not used, the EF pin can be either tied to ground
or left open. If this function is used, a 10 kΩ, or larger, pull-up
resistor (R₂ in Figure 2) is recommended. The larger the
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