LMH7220_0805 Datasheet, PDF (16/20 Pages) National Semiconductor (TI) – High Speed Comparator with LVDS Output

absolute value of the difference between both voltages is
called V_OD. LVDS outputs cannot be held at the V_O level be-
cause of their digital nature. They only cross this level during
a transition. Due to the symmetrical structure of the circuit,
both output voltages cross at V_O regardless if the output
changes from ‘0’ to ‘1’ or vise versa.
comparator’s outputs. In the case of a balanced input con-
nected to the load resistance, current I_P is drawn from both
output connection points to ground. Keep in mind that the
LMH7220’s ability to source currents is much higher than to
sink them. The connected input circuitry also forms a differ-
ential load to the outputs of the comparator (see Figure 14).
This will cause the voltage across the termination resistor to
differ from its nominal value.
FIGURE 12. LVDS Output Signals
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In case the outputs aren’t symmetrical or are a-symmetrically
loaded, the output voltages differ from the situation of Figure
12. For this non-ideal situation there are two additional pa-
rameters defined, ΔV_O and ΔV_OD, as can be seen in Figure
13.
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FIGURE 13. LVDS Output Signals with Different
Amplitude
ΔV_O is the difference in V_O between the ‘1’ state and the ‘0’
state. This variation is acceptable if it is below 50 mV following
the ANSI/TIA/EIA-644 LVDS standard. It is also possible that
V_OD in the ‘1’ state isn’t the same as in the ‘0’ state. This pa-
rameter is specified as ΔV_OD, and is calculated as the abso-
lute value of the difference of V_ODH and V_ODL.
LOADING THE OUTPUT
The output structure creates a current (I_LOOP see Figure 14)
through an external differential load resistor of 100Ω nominal.
This results in a differential output voltage of 325 mV. The
outputs of the comparator are connected to tracks on a PCB.
These tracks can be seen as a differential transmission line.
The differential load resistor acts as a high frequency termi-
nation at the end of the transmission line. This means that for
a proper signal behavior the PCB tracks have to be dimen-
sioned for a characteristic impedance of 100Ω as well.
Changing the load resistor also implies a change of the trans-
mission line impedance. More about transmission lines and
termination can be found in the next section. The signal
across the 100Ω termination resistor is fed into the inputs of
subsequent circuitry that processes the data. Any connection
to input circuitry of course draws current from the
FIGURE 14. Load
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In general one single connection only draws a few µA’s, and
doesn’t have much effect on the LVDS output voltage. For
multiple inputs on one output pair, load currents must not ex-
ceed the specified limits, as described in the ANSI or IEEE
LVDS standards. Below a specified value of V_OD, the func-
tioning of subsequent circuitry becomes uncertain. However
under normal conditions there is no need to worry. Another
point of practice is load capacitances. Capacitances are ap-
plied differentially (C_LOAD) and also to ground (C_P). All of these
capacitors will disturb the pulse shape. The edges of the out-
put pulse become slower, and in reaction the detection of the
transition comes at a later moment. Be aware of this effect
when measuring with probes. Both single ended and differ-
ential probes have these capacitances. A standard probe
commonly has a load capacity of about 8 to 10 pF. This will
cause some degradation of the pulse shape and will add
some time delay.
TRANSMISSION LINES & TERMINATION
TECHNOLOGIES
The LMH7220 uses LVDS technology. LVDS is a way to com-
municate data using low voltage swing and low power con-
sumption. Nowadays data rates are growing, requiring
increasing speed. Data isn’t only connected to other IC’s on
a single PCB board but in many cases there are interconnec-
tions from board to board or from equipment to equipment.
Distances can be short or long but it is always necessary to
have a reliable connection, consume low power and to be able
to handle high data rates. LVDS is a differential signal proto-
col. The advantage over single ended signal transmission is
its higher immunity to common mode noise. Common mode
signals are signals that are equally apparent on both lines and
because the receiver only looks at the difference between
both lines, this noise is canceled.
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