LMH7220_0805 Datasheet, PDF (11/20 Pages) National Semiconductor (TI) – High Speed Comparator with LVDS Output

DEFINITIONS
For a good understanding of many parameters of the
LMH7220 it is necessary to perform a lot of measurements.
All of those parameters are listed in the data tables in the first
part of the datasheet. There are different tables for several
supply voltages containing a separate set of data per supply
voltage. In the table below is a list of abbreviations of the
measured parameters and a short description of the condi-
tions which are applied for measuring them . Following this
table several parameters are highlighted to explain more
clearly what it means exactly and what effects such a phe-
nomena can have for any applied electronic circuit.
Symbol
I_B
I_OS
TC I_OS
V_OS
TC V_OS
CMRR
VRI
PSRR
V_O
ΔV_O
V_OH
V_OL
V_ODH
V_ODL
V_OD
ΔV_OD
Hyst
I_SQG, I_SQG
I_SQQ
TR
PW
t_PDH resp t_PDL
t_PDL resp t_PDH
t_PDLH
t_PDHL
t_PD
Text
Description
Input Bias Current
Current flowing in or out the input pins, when both biased at 0.3 Volt
above GND
Input Offset Current
Difference between the positive- and the negative input currents
needed to make the outputs change state, averaged for H to L and L
to H transitions
Average Input Offset Current Drift
Input Offset Voltage
Temperature Coefficient of I_OS
Voltage difference needed between IN⁺ and IN^− to make the outputs
change state, averaged for H to L and L to H transitions
Average Input Offset Voltage Drift
Common Mode Rejection Ratio
Temperature Coefficient of V_OS
Ratio of input offset voltage change and input common mode voltage
change
Input Voltage Range
Upper and lower limits of the input voltage are defined as where
CMRR drops below 50 dB.
Power Supply Rejection Ratio
Output Offset Voltage
Ratio of input offset voltage change and supply voltage change from
V_S-MIN to V_S-MAX
Output Common Mode Voltage averaged for logic ‘0’ and logic ‘1’
levels (See Figure 12)
Change in Output Offset Voltage
Difference in Output Common Mode Voltage between logic ‘0’ and
logic ‘1’ levels (See Figure 13)
Output Voltage High
High state single ended output voltage (Q or Q) (See Figure 12)
Output Voltage Low
Low state single ended output voltage (Q or Q) (See Figure 12)
Output Differential Voltage logic ‘1’
Output Differential Voltage logic ‘0’
Average of V_ODH and V_ODL
Change in V_OD between ‘0’ and ‘1’
Hysteresis
V_OH(Q) – V_OL(Q) (logic level ‘1’) (See Figure 13)
V_OH(Q) – V_OL(Q) (logic level ‘0’) (See Figure 13)
(V_ODH + V_ODL) / 2
|V_ODH – V_ODL| (See Figure 13)
Difference in input switching levels for L to H and H to L transitions.
(See Figure 11)
Short Circuit Current one output to
GND
Current that flows from one output to GND if shorted single ended
Short Circuit Current outputs together Current flowing between output Q and output Q if shorted differentially
Maximum Toggle Rate
Maximum frequency at which the outputs can toggle before V_OD drops
under 50% of the nominal value.
Pulse Width
Time from 50% of the rising edge of a signal to 50% of the falling edge
Propagation Delay
Delay time between the moment the input signal crosses the switching
level L to H and the moment the output signal crosses 50% of the
rising edge of Q output (t_PDH), or delay time between the moment the
input signal crosses the switching level H to L and the moment the
output signal crosses 50% of the falling edge of Q output (t_PDL)
Delay time between the moment the input signal crosses the switching
level L to H and the moment the output signal crosses 50% of the
falling edge of Q output (t_PDL), or delay time between the moment the
input signal crosses the switching level H to L and the moment the
output signal crosses 50% of the rising edge of Q output (t_PDH)
Average of t_PDH and t_PDL
Average of t_PDL and t_PDH
Average of t_PDLH and t_PDHL
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