LMH7220_0805 Datasheet, PDF (15/20 Pages) National Semiconductor (TI) – High Speed Comparator with LVDS Output

Using Hysteresis
A good way to avoid oscillations and noise during slow slopes
is the use of hysteresis. For this purpose a threshold is intro-
duced that pushes the input switching level back at the mo-
ment the output switches (See Figure 10). In this simple
setup, a comparator with a single output and a resistive di-
vider to the positive input is drawn.
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FIGURE 10. Simplified Schematic
The divider R_F-R_P feeds back a portion of the output voltage
to the positive input. Only a small part of the output voltage is
needed, just enough to avoid the area at which the input is in
an undefined state. Assuming this is only a few millivolts, it is
sufficient to add (plus or minus) 10 mV to the positive input to
prevent the circuit from oscillations. If the output switches be-
tween 0V and 5V and the choice for one of the resistors is
done the other can be calculated. Assume R_P is 50Ω then
R_F is 25 kΩ for 10 mV threshold on the positive input. The
situation of Figure 11 is now created.
FIGURE 11. Hysteresis
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In this picture there are two dotted lines A and B, both indi-
cating the resulting level at the positive input. When the signal
at the negative input is low, the state of the input stage is well
defined with the negative input much lower than the positive
input. As a result the output will be in the high state. The pos-
itive input is at level A. With the input signal sloping up, this
situation remains until V_IN crosses level A at t=1. Now the
output toggles, and the voltage at the positive input is lowered
to level B. So before the output has the possibility to toggle
again, the difference between both inputs is made sufficient
to have a stable situation again. When the input signal comes
down from high to low, the situation is stable until level B is
reached at t=0. At this moment the output will toggle back,
and the circuit is back in the start situation with the negative
input at a much lower level than the positive one. In the situ-
ation without hysteresis, the output would toggle exactly at
V_REF. With hysteresis this happens at the introduced levels A
and B, as can be seen in Figure 11. Varying the levels A and
B will also vary the timing of t=0 and t=1. When designing a
circuit be aware of this effect. Introducing hysteresis will
cause some time shifts between output and input (e.g. duty
cycle variations), but eliminates undesired switching of the
output.
Parasitic Capacitors
In the simple schematic of Figure 10 some capacitors are
drawn. The capacitors C_P. represent the parasitic (board) ca-
pacitance at the input of the part. This capacity will slow down
the change of the level of the positive input in reaction to the
changing output voltage. As a result of this, the output may
have the time to switch over more than once. Actually the
parasitic capacity represented by C_P makes the attenuation
circuit of R_F and R_P frequency dependent. The only action to
take is to create a frequency independent circuit. This is sim-
ply done by placing the compensation capacitor C_C in parallel
with R_F. The capacitor C_C can be calculated with the formula
R_F *C_C = R_P *C_P, this means that both of the time constants
must be the same to create a frequency independent network.
A simple example gives the following assuming that C_P is in
total 2.5 pF and as already calculated R_F = 25 kΩ in combi-
nation with R_P = 50Ω. These input data gives:
C_C = R_P * C_P/R_F
C_C = 50*2.5e-12/25e3
C_C = 5e-15 = 0.005 pF
This is not a practical value and different conclusions are
possible:
• No capacitor C_C needed
• Place a capacitor C_C of 1 pF and accept a big overshoot
at the positive input being sure that the input stage is in a
secure new position
• Place an extra C_P of such a value that C_C has a realistic
value of say 1 pF (extra C_P = ±500 pF).
Position of Feedback Resistors
Another important issue while using positive feedback is the
placement of the resistors R_P and R_F. These resistors must
be placed as near as possible to the positive input, because
this input is most sensitive for picking up spurious signals,
noise etc. This connection must be very clean for the best
performance of the overall circuit. With raising speeds the to-
tal PCB design becomes more and more critical, the
LMH7220 comparator doesn’t have built in hysteresis, so the
input signal must meet minimum requirements to make the
output switch over properly. In the following sections some
aspects concerning the load connected to the outputs and
transmission lines will be discussed.
THE OUTPUT SWING PROPERTIES
LVDS has differential outputs which means that both outputs
have the same swing but in opposite direction (Figure 12).
Both outputs swing around a voltage called the common
mode output voltage (V_O). This voltage can be measured at
the midpoint of two equal resistors connected to both outputs
as discussed in the section ‘Input and Output Topology’. The
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