LMH6502 Datasheet, PDF (15/19 Pages) National Semiconductor (TI) – Wideband, Low Power, Linear-in-dB Variable Gain Amplifier

Application Information (Continued)
V_IN = 0V, the input referred V_OS term shows up as a small
square wave riding a DC value. Adjust R₁₀ to null the V_OS
square wave term to zero. After adjusting the input-referred
offset, adjust R₁₄ (with V_IN = 0, V_G = 0) until V_OUT is zero.
Finally, for inverting applications V_IN may be applied to pin 6
and the offset adjustment to pin 3. These steps will minimize
the output offset voltage. However, since the offset term itself
varies with the gain setting, the correction is not perfect and
some residual output offset will remain at in-between V_G’s.
Also, this offset trim does not improve output offset tempera-
ture coefficient.
NOISE
Figure 3 describes the LMH6502’s output-referred spot
noise density as a function of frequency with A_VMAX = 10V/V.
The plot includes all the noise contributing terms. However,
with both inputs terminated in 50Ω, the input noise contribu-
tion is minimal. At A_VMAX = 10V/V, the LMH6502 has a typical
input-referred spot noise density (e_in) of 7.7nV/
flat-
band. For applications extending well into the flat-band re-
gion, the input RMS voltage noise can be determined from
the following single-pole model:
(5)
20067743
FIGURE 2. Nulling the output offset voltage
GAIN ACCURACY
Defined as the actual gain compared against the theoretical
gain at a certain V_G (results expressed in dB).
Theoretical gain is given by:
(4)
Where K = 1.72 (nominal) & V_C = 90mV @ room tempera-
ture.
For a V_G range, the value specified in the tables represents
the worst case accuracy over the entire range. The "Typical"
value would be the worst case difference between the "Typi-
cal Gain" and the "Theoretical gain". The "Max" value would
be the worst case difference between the max/min gain limit
and the "Theoretical gain".
GAIN MATCHING
Defined as the limit on gain variation at a certain V_G (ex-
pressed in dB). Specified as "Max" only (no "Typical"). For a
V_G range, the value specified represents the worst case
matching over the entire range. The "Max" value would be
the worst case difference between the max/min gain limit
and the typical gain.
20067710
FIGURE 3. Output Referred Voltage Noise vs.
Frequency
CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION
BOARD
A good high frequency PCB layout including ground plane
construction and power supply bypassing close to the pack-
age are critical to achieving full performance. The amplifier is
sensitive to stray capacitance to ground at the I^− input (pin
12); keep node trace area small. Shunt capacitance across
the feedback resistor should not be used to compensate for
this effect. For best performance at low maximum gains
(A_VMAX < 10) +R_G and -R_G connections should be treated in
a similar fashion. Capacitance to ground should be mini-
mized by removing the ground plane from under the body of
R_G.. Parasitic or load capacitance directly on the output (pin
10) degrades phase margin leading to frequency response
peaking.
The LMH6502 is fully stable when driving a 100Ω load. With
reduced load (e.g. 1kΩ) there is a possibility of instability at
very high frequencies beyond 400MHz especially with a
capacitive load. When the LMH6502 is connected to a light
load as such, it is recommended to add a snubber network to
the output (e.g. 100Ω and 39pF in series tied between the
LMH6502 output and ground). C_L can also be isolated from
the output by placing a small resistor in series with the output
(pin 10).
Component parasitics also influence high frequency results.
Therefore it is recommended to use metal film resistors such
as RN55D or leadless components such as surface mount
devices. High profile sockets are not recommended.
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