LMH6628EP Datasheet, PDF(10/16 Page) National Semiconductor (TI) – Enhanced Plastic Dual Wideband, Low Noise, Voltage Feedback Op Amp

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LMH6628EP Datasheet, PDF (10/16 Pages) National Semiconductor (TI) – Enhanced Plastic Dual Wideband, Low Noise, Voltage Feedback Op Amp

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2-Tone, 3rd Order Intermodulation Intercept

Voltage & Current Noise vs. Frequency

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Settling Time vs. Accuracy

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Application Section

LOW NOISE DESIGN

Ultimate low noise performance from circuit designs using the

LMH6628EP requires the proper selection of external resis-

tors. By selecting appropriate low valued resistors for RF and

RG, amplifier circuits using the LMH6628EP can achieve out-

put noise that is approximately the equivalent voltage input

noise of 2nV/ multiplied by the desired gain (AV).

DC BIAS CURRENTS AND OFFSET VOLTAGES

Cancellation of the output offset voltage due to input bias cur-

rents is possible with the LMH6628EP. This is done by making

the resistance seen from the inverting and non-inverting in-

puts equal. Once done, the residual output offset voltage will

be the input offset voltage (VOS) multiplied by the desired gain

(AV). National Application Note OA-7 offers several solutions

to further reduce the output offset.

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OUTPUT AND SUPPLY CONSIDERATIONS

With Â±5V supplies, the LMH6628EP is capable of a typical

output swing of Â±3.8V under a no-load condition. Additional

output swing is possible with slightly higher supply voltages.

For loads of less than 50â¦, the output swing will be limited by

the LMH6628EP's output current capability, typically 85mA.

Output settling time when driving capacitive loads can be im-

proved by the use of a series output resistor. See the plot

labeled "RS vs. CL" in the Typical Performance section.

LAYOUT

Proper power supply bypassing is critical to insure good high

frequency performance and low noise. De-coupling capaci-

tors of 0.1Î¼F should be placed as close as possible to the

power supply pins. The use of surface mounted capacitors is

recommended due to their low series inductance.

A good high frequency layout will keep power supply and

ground traces away from the inverting input and output pins.

Parasitic capacitance from these nodes to ground causes fre-

quency response peaking and possible circuit oscillation. See

OA-15 for more information. National suggests the 730036

www.national.com

200886 Version 4 Revision 2 Print Date/Time: 2010/10/15 15:22:20

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