SM5170AV Datasheet, PDF (8/10 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5170AV
Input data format example
Reference frequency divider = 144, LD normal operation:
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
2 ¹⁵ 2 ¹⁴ 2 ¹³ 2 ¹² 2 ¹¹ 2 ¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰
000000001001000000010001
Reference Counter (16bit : 5 to 65535) _{Not used (set to 000)}
LDpin Set bit
Test bits (set to 00)
Control bits
Figure 6. Reference counter data and LD output setting example
Standby Mode
The SM5170AV enters standby mode when OPR
goes LOW. In this mode, the states and functions
shown in the table occur.
Block
DO and DB
LD
Phase comparator
Input FIN
Input XIN
N counter
R counter
Latch data
State
Floating (high impedance)
L OW -level output
Reset
Feedback resistor is cutoff (HIGH level)
Feedback resistor is cutoff (HIGH level)
Reset
Reset
Stored (while V _DD2 is within rating)
In standby mode, some current flows into VDD1.
Therefore, it is necessary to reduce V_DD1 to 0 V to
fully reduce current consumption and reduce power
dissipation. Note that if both the V_DD1 and V_DD2
supplies are reduced to 0 V, the latch contents will be
erased. In this case, V_DD1 only should be reduced to
0 V.
Standby mode is released when V_DD1 rises and OPR
goes HIGH.
Phase Comparator Timing Diagram
FR
FV
DO
LD
Figure 7. Phase comparator timing
The DO output circuit polarity is configured for con-
nection to an external passive filter.
The signals compared are FV and FR, which are the
internal FIN input frequency divider output signal
and reference frequency divider output signal,
respectively.
NIPPON PRECISION CIRCUITS—8