SM5170AV Datasheet, PDF (6/10 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5170AV
Swallow counter and main counter data
The swallow counter and main counter which deter-
mine the FIN input frequency divider ratio are set by
bits 1 to 12 and bits 13 to 17, respectively. The volt-
age signal output on pin DB is set by bits 18 to 22.
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
2 ¹¹ 2 ¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰
Main Counter
(12bit : 32 to 4095)
Swallow Counter
(5bit : 0 to 31)
DBpin Condition Select bits
Control bits
Figure 3. Swallow counter and main counter frequency divider data format
FIN input frequency divider example
If the VCO output is (f_VCO), the output frequency
(f_LO) is 251.3 MHz, and the channel bandwidth (f_CH:
Phase comparator frequency (f_R)) is 25 kHz, then the
FIN input frequency divider ratio N is given by:
N = -f--^L----^O-- = -f--^V----^C----^O-- = ^{2---5---1---.--3-} = 10052
f_CH f_N 0.025
= 32 × 314 + 4
Therefore, the swallow counter count is 4 (00100)₂
and the main frequency divider counter count is 314
(000100111010)₂ .
DB fast-lockup data
The output voltage on pin DB provides an additional
boost to charge the external lowpass filter capacitor
for faster lockup times. One of 31 possible output
voltage level signals is selected by bits 18 to 22.
The DB level signal output occurs during 2 clock
cycles when the reference frequency divider compar-
ator signal FR is generated after OPR goes HIGH, or
after LE goes LOW when data is written. The DB
output subsequently becomes high impedance.
Note that if bits 18 to 22 are all set to 0, this function
is not activated and DB remains in the high imped-
ance state.
Input data format example
FIN input frequency divider = 10052, DB is high impedance:
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
2 ¹¹ 2 ¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰
000100111010001000000000
Main Counter
(12bit : 32 to 4095)
Control bits
Swallow Counter
(5bit : 0 to 31)
DBpin Condition Select bits
Figure 4. Swallow counter and main counter frequency divider data example
NIPPON PRECISION CIRCUITS—6