SM5170AV Datasheet, PDF (4/10 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5170AV
Electrical Characteristics
V_SS = 0 V, V_DD1 = 0.95 to 1.2 V, V_DD2 = 2.0 to 3.3 V, T_a = −10 to 60 °C
Parameter
Symbol
Condition
Rating
Unit
min
typ
max
VDD1 operating current consumption
VDD2 operating current consumption
VDD1 standby current
VDD2 standby current
FIN maximum operating input frequency
XIN maximum operating input frequency
FIN minimum operating input frequency
XIN minimum operating input frequency
FIN input amplitude
I_{D D 1} Note 1.
I_{D D 2} Note 2.
–
1.1
1.9
mA
–
0.003
–
I_st1 Note 3.
I_st2 Note 4.
–
0.7
–
µA
–
0.01
10.0
f_{m a x 1}
300 mVp-p sine
w ave
V_DD1 = 0.95 to 1.2 V
V_DD1 = 1.0 to 1.2 V
300
330
–
–
–
MHz
–
f_max2 300 mVp-p sine wave (external input)
25
–
–
MHz
f_min1 300 mVp-p sine wave
–
–
40
MHz
f_min2 300 mVp-p sine wave (external input)
–
–
9
MHz
V _FIN1
V _FIN2
f_FIN = 300 MHz, AC coupling
f_FIN = 330 MHz, V _{D D 1} = 1.0 to 1.2 V,
AC coupling
0.3
–
0.3
–
–
Vp-p
–
XIN input amplitude
OPR, CLK, DATA, LE LOW -level input
voltage
V _XIN f_XIN = 25 MHz, AC coupling (external input)
0.3
–
–
Vp-p
V _IL
–
–
0.3
V
OPR, CLK, DATA, LE HIGH-level input
voltage
V _IH
V_DD2 −
0.3
–
–
V
FIN LOW -level input current
XIN LOW -level input current
FIN HIGH-level input current
XIN HIGH-level input current
DB LOW -level output voltage
DB HIGH-level output voltage
I_IL1
I_IL2
I_{I H 1}
I_{I H 2}
V _DOL
V _DOH
V _IL = 0 V
V_IH = V_DD1
Note 5.
Note 6.
–
–
–
–
–
–
–
–
V_DD2 −
0.5
60
µA
10
µA
60
µA
10
µA
0.5
V
V
D O L OW -level output current
DO HIGH-level output current
D O, DB tristate output high-impedance
leakage current
D ATA → CLK setup time
CLK → LE setup time
Hold time
I_{D O L} Note 7.
I_{D O H} Note 8.
I_{O Z L} V _{O L} = 0 V
I_{O Z H} V _{O H} = V _{D D 2}
t_{S U 1}
t_{S U 2} See the timing diagra m s .
t_H
1.0
–
–
mA
1.0
–
–
mA
–
–
100
nA
–
–
100
nA
2
–
–
µs
2
–
–
µs
2
–
–
µs
1. V _{D D 1} = 1.0 to 1.05V, V _{D D 2} = 2.7 to 3.3 V, f_FIN = 310 MHz (300 mVp-p sine wave), f_XIN = 14.4 MHz (300 mVp-p sine wave), 25 kHz comparator fre-
quency, OPR = HIGH, no output load, typ condition : V _{D D 1} = 1.0 V
2. V _{D D 1} = 0.95 to 1.2 V, V _{D D 2} = 2.7 to 3.3 V, f_FIN = 310 MHz (300 mVp-p sine wave), f_XIN = 14.4 MHz (300 mVp-p sine wave), 25 kHz comparator fre-
quency, OPR = HIGH, no output load, typ condition : V _{D D 2} = 3.0 V
3. V _DD1 = 1.0 V, V _DD2 = 3.0 V, OPR = LOW , no input/output load (i.e. CLK = DATA = LE = 0 V)
4. V _DD1 = 0 V, V _DD2 = 2.7 to 3.3 V, OPR = LOW , no input/output load (i.e. CLK = DATA = LE = 0 V), typ condition : V _DD2 = 3.0 V
5. DB output is derived from the V _{D D 2} supply. DB-pin condition select bit = (00001)₂ , V _{D D 2} = 2.7 to 3.3 V, no load
6. DB output is derived from the V _{D D 2} supply. DB-pin condition select bit = (11111)₂ , V _{D D 2} = 2.7 to 3.3 V, no load
7. DO output is derived from the V _{D D 2} supply. V _{D D 2} = 2.7 to 3.3 V, V _{O L} = 0.4 V
8. DO output is derived from the V _{D D 2} supply. V _{D D 2} = 2.7 to 3.3 V, V _{O H} = V _{D D 2} − 0.4 V
DATA, CLK, and LE timing
DATA
VIH
tSU1
VIH
tH
CLK
VIH
tSU2
LE
VIH
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