SM5170AV Datasheet, PDF (7/10 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5170AV
Reference Frequency Divider (R-counter) Structure
The reference frequency divider generates a compar-
ator frequency signal (FR), which is input to the
phase comparator, by dividing the reference oscilla-
tor frequency input either from an external signal on
XIN or from a crystal oscillator connected between
XIN and XOUT.
The reference frequency divider is comprised of a
fixed divide-by-4 prescaler and a 16-bit reference
counter.
Frequency settings Prescaler
Reference counter
Reference frequency divider ratio
Counter set ranges Prescaler
Reference counter
Reference frequency divider ratio range
A (= 4)
B
R=A×B=4×B
A=4
B = 5 to 65535
R = 20 to 262140
Reference counter frequency data and LD setting
The reference counter which determines the refer-
ence frequency divider ratio is set by bits 1 to 16.
The lock detect signal output is set by bit 20.
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
2 ¹⁵ 2 ¹⁴ 2 ¹³ 2 ¹² 2 ¹¹ 2 ¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰
Reference Counter (16bit : 5 to 65535) _{Not used (set to 000)}
LDpin Set bit
Test bits (set to 00)
Control bits
Figure 5. Reference counter data and LD output setting format
Reference frequency divider example
If the VCO output is (f_VCO), the crystal oscillator
frequency is 14.4 MHz and the channel bandwidth
(f_CH: comparator frequency (f_R)) is 25 kHz, then the
reference frequency divider ratio R is given by:
R
=
-X----t--a---l
f_CH
=
X-----t--a---l
f_R
=
0--1-.--40---.2-4--5-
=
576
=
4 × 144
Therefore, the reference counter count is 144
(0000000010010000)₂ .
LD output
The output on LD is set by bit 20.
Bit 20
1
0
LD output
Normal unlock signal output (normal operation)
Unlock signal output OFF, LOW -level output
Bits 15 to 19, bits 21 to 22
Bits 15 to 19 have no meaning, and should be set to
0. Bits 21 and 22 are factory test bits and should also
be set to 0.
NIPPON PRECISION CIRCUITS—7