SM9403BM Datasheet, PDF (7/18 Pages) Nippon Precision Circuits Inc – DVDRAM Servo-amplifier LSI

SM9403BM
DPD Error Signal Detector Characteristics (DPDA/DPDB/DPDC/DPDD → TRP)
V_CC = 5V ± 5%, GND = 0V, T_a = 0 to 70°C
Parameter¹
Condition
Rating
Unit
min
typ
max
DPDA/DPDB/DPDC/DPDD input voltage
ra n g e
VREF2 reference
−0 . 5 5
–
+1
V
DPDA/DPDB/DPDC/DPDD input
impedance
1
–
–
MΩ
Signal gain relative accuracy
Gain relative to DPDA, DPDB, DPDC,
DPDD inputs
–
–
±0.17
dB
Equalizer gain
1MHz setting
5MHz setting
DG2 =LOW
DG2 = HIGH
DG2 =LOW
DG2 = HIGH
1.2
1.6
2.3
1.8
2.2
2.9
dB
5.5
6.1
6.6
6.1
6.7
7.2
Equalizer frequency response
Peak gain frequency (EQE = HIGH)
−3dB frequency (EQE = LOW )
3.75
5.0
6.25
MHz
11
22
33
Equalizer frequency response relative
accuracy
f_peak, (A + C) vs. (B + D)
–
–
±1.5
%
A C coupling time circuit −3dB frequency
Time constant 1
Time constant 2
DG2 = LOW
DG2 = HIGH
56
84
109
kHz
17
24
32
AC coupling time constant relative
accuracy
−3dB frequency, (A + C) vs. (B + D)
–
–
±2
%
Delay control range
See table 4.
See table 4.
ns
Phase difference detector minimum time DG1 = DG2 = LOW
2
–
–
ns
Phase difference detector maximum time DG1 = DG2 = HIGH
–
–
1
µs
Phase difference detector minimum
repeat time
Input pulse interval
120
–
–
ns
Phase difference to voltage conversion
coefficient
DG1 = DG2 = LOW
–
See table 5. typ ± 20% mV/ns
Phase difference to voltage conversion
coefficient change accuracy
–
See table 8.
±1
dB
Phase difference output offset voltage VREF2 reference
–
–
±0.1
V
Phase difference output offset voltage
temperature drift
VREF2 reference
–
–
±570
µ V / °C
DEFECT signal response time
–
–
1
µs
DPD enable response time
DPE flag
–
–
2
µs
Abnormal waveform TRP droop
characteristic
V _{O U T} = V _{R E F 2} ± 200mV, VREF2 reference
–
–
0.1
%/µs
TRP output voltage range
VREF2 reference
−1 . 2 5
0
+1.25
V
TRP output signal frequency response −3dB frequency
500
–
–
kHz
1. The tracking error signal TRE is positive with respect to VREF2 if the (DPDA + DPDC) signal phase difference is leading.
The detected phase difference is the difference between the point when one internal comparator output changes (from CMA and CMB both HIGH or
both LOW) until the second output changes before the first changes again. The phase difference is converted to a voltage and sampled for output.
Other signals are held constant in the output stage when a phase difference is detected.
NIPPON PRECISION CIRCUITS—7