SM9403BM Datasheet, PDF (13/18 Pages) Nippon Precision Circuits Inc – DVDRAM Servo-amplifier LSI

SM9403BM
Table 4. DPD delay time settings
DPD delay (ns)¹
DG2 DG1 DL4 DL3 DL2 DL1
min typ max
LOW LOW LOW LOW 0 0 0
L O W L O W L O W H I G H −2.2 −3.0 −3.3
L O W L O W H I G H L O W −4.2 −5.6 −6.4
L O W L O W H I G H H I G H −6.0 −8.0 −9.5
L O W H I G H L O W L O W −7.5 −11 −13
L O W H I G H L O W H I G H −10 −14 −16
L O W H I G H H I G H L O W −12 −17 −20
L O W H I G H H I G H H I G H −14 −20 −24
LOW LOW
HIGH LOW LOW LOW +17 +24 +29
HIGH LOW LOW HIGH +14 +20 +23
HIGH LOW HIGH LOW +12 +17 +19
HIGH LOW HIGH HIGH +10 +13 +15
HIGH HIGH LOW LOW +7.5 +11 +13
HIGH HIGH LOW HIGH +5.6 +7.7 +9.0
HIGH HIGH HIGH LOW +3.7 +5.5 +6.2
HIGH HIGH HIGH HIGH +2.0 +3.0 +3.4
LOW LOW LOW LOW 0 0 0
L O W L O W L O W H I G H −3.8 −4.5 −6.0
L O W L O W H I G H L O W −7.0 −8.5 −11
L O W L O W H I G H H I G H −11 −13 −17
L O W H I G H L O W L O W −16 −18 −24
L O W H I G H L O W H I G H −20 −23 −32
L O W H I G H H I G H L O W −26 −30 −42
L O W H I G H H I G H H I G H −34 −38 −55
LOW HIGH
HIGH LOW LOW LOW +44 +49 +74
HIGH LOW LOW HIGH +33 +37 +52
HIGH LOW HIGH LOW +25 +29 +38
HIGH LOW HIGH HIGH +20 +22 +29
HIGH HIGH LOW LOW +15 +17 +22
HIGH HIGH LOW HIGH +10 +12 +17
HIGH HIGH HIGH LOW +7.0 +7.9 +11
HIGH HIGH HIGH HIGH +3.6 +4.3 +5.6
Table 4. DPD delay time settings (Continued)
DPD delay (ns)¹
DG2 DG1 DL4 DL3 DL2 DL1
min typ max
LOW LOW LOW LOW 0 0 0
L O W L O W L O W H I G H −7.0 −8.5 −13
L O W L O W H I G H L O W −15 −17 −24
L O W L O W H I G H H I G H −22 −27 −36
L O W H I G H L O W L O W −32 −37 −50
L O W H I G H L O W H I G H −43 −48 −65
L O W H I G H H I G H L O W −55 −62 −83
L O W H I G H H I G H H I G H −70 −78 −108
HIGH LOW
HIGH LOW LOW LOW +90 +100 +136
HIGH LOW LOW HIGH +70 +78 +102
HIGH LOW HIGH LOW +55 +61 +76
HIGH LOW HIGH HIGH +42 +47 +60
HIGH HIGH LOW LOW +31 +36 +45
HIGH HIGH LOW HIGH +22 +26 +34
HIGH HIGH HIGH LOW +14 +17 +23
HIGH HIGH HIGH HIGH +7.2 +8.2 +12
LOW LOW LOW LOW 0 0 0
L O W L O W L O W H I G H −9.5 −11 −17
L O W L O W H I G H L O W −19 −22 −32
L O W L O W H I G H H I G H −30 −35 −49
L O W H I G H L O W L O W −42 −48 −74
L O W H I G H L O W H I G H −60 −67 −105
L O W H I G H H I G H L O W −80 −90 −150
L O W H I G H H I G H H I G H −110 −122 −205
HIGH HIGH
HIGH LOW LOW LOW +124 +167 +210
HIGH LOW LOW HIGH +108 +120 +194
HIGH LOW HIGH LOW +80 +88 +130
HIGH LOW HIGH HIGH +58 +65 +90
HIGH HIGH LOW LOW +42 +47 +64
HIGH HIGH LOW HIGH +29 +33 +45
HIGH HIGH HIGH LOW +18 +21 +31
HIGH HIGH HIGH HIGH +9.0 +10 +16
1. Default is 0 ns (DL4 = DL3 = DL2 = DL1 = LOW)
The DPD delay is positive when (A+C) leads (B+D).
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