SM3320AGA Datasheet, PDF (7/15 Pages) Nippon Precision Circuits Inc – Dark current compensation circuit built-in for stable signal output

SM3320AGA
AC Characteristics
Data Write Mode
Parameter
Recommended operating conditions using reference circuit, unless otherwise noted.
Symbol
Conditions
MIN TYP MAX Unit
Write clock LOW-level pulse width
twlw CLK pin
40
-
Write clock HIGH-level pulse width
twhw CLK pin
40
-
Data setup time 1
tsu1 Between SE-CLK
40
-
Data setup time 2
tsu2 Between DATA-CLK
40
-
Data hold time 1
th1 Between SE-CLK
140
-
Data hold time 2
th2 Between DATA-CLK
40
-
Write clock frequency
fclkw
-
-
Settling time
Output disable time^*1
Input capacitance^*2
Output capacitance^*2
Interface wait time
OUT pin, 100pF load, 1V output
tst
amplitude variation, time to
-
-
reach 95% level
tz
OUT pin
-
0.1
C_I
SE,OE,CLK,DATA pins
-
5
C_O
OUT pin
-
5
tsi
100
-
*1. Design value: Provided as a measure for the output control time.
*2. Design value: Indicates the terminal capacitance per pin. Provided as a guide for when designing the circuit board.
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
10
MHz
2
μs
-
μs
-
pF
-
pF
-
ns
LOW/HIGH-level switch timing measured with respect to 0.5V_DD reference level, unless otherwise noted.
OE
tsi
SE
DATA
CLK
OUT
Data Read Mode
R/W
tsu2
1
tsu1
Parameter
Read clock LOW-level pulse width
Read clock HIGH-level pulse width
Read clock frequency
SE hold time
Read-out data delay time
A2
A1
twhw twlw
2
3
1/fclkw
GS1
th2
15
GS0
th1
16
tst
95%
tz
100%
Recommended operating conditions using reference circuit, unless otherwise noted.
Symbol
Conditions
MIN TYP MAX Unit
twlr CLK pin
500
-
-
ns
twhr CLK pin
500
-
-
ns
fclkr
-
-
1
MHz
tse Between SE-CLK
500
-
-
ns
tRD DATA pin, load capacitance=100pF
-
-
400
ns
LOW/HIGH-level switch timing measured with respect to 0.5V_DD reference level, unless otherwise noted.
OE
"L" or open
SE
DATA
CLK
R/W
A2
A1
1
2
3
-
CS1
CS0
tZZ
tRD
7
8
9
GS1
GS0
-
twhr twlr
tse
15
16
1/fclkr
SEIKO NPC CORPORATION - 7