SM3320AGA Datasheet, PDF (11/15 Pages) Nippon Precision Circuits Inc – Dark current compensation circuit built-in for stable signal output

SM3320AGA
Reading Data from the Register (OE = LOW or open-circuit)
Serial interface operation starts when SE goes HIGH.
Read data comprises 1 read/write mode bit (read mode = 1), 3 address bits, and 4 dummy data bits transferred in sequence when OE is
open-circuit or goes LOW. The address control pin setting is compared with the address register setting on the falling edge of the 8^th CLK
pulse. If the settings match (meaning the device is addressed), the data in the 8-bit analog adjustment code register is read out in sequence.
On the serial interface, the GS0 data bit is transferred on the 15^th falling edge of CLK, and then any data bits transferred between the 16^th
falling edge of CLK and the falling edge on SE are undefined data. Serial interface operation ends when SE goes LOW, and the DATA
terminal reverts to an input. Make sure there are not less than nor more than 16 input pulses on the CLK clock. If the number of clock
pulses is incorrect, incorrect data may be written to the register or read from the register.
Register read
SE
DATA
CLK
R/W A2 A1 A0 - - - - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 -
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SEIKO NPC CORPORATION - 11