SM3320AGA Datasheet, PDF (10/15 Pages) Nippon Precision Circuits Inc – Dark current compensation circuit built-in for stable signal output

SM3320AGA
Gain Setting (register write mode, OE = LOW or open-circuit)
If OE is LOW or open circuit, serial interface operation starts when SE goes HIGH.
Write data comprises 1 read/write mode bit (write mode = 0), 3 address bits, and 12 write data bits transferred in sequence. If the address
data bits match the address control pin settings (meaning the device is addressed), the write data is loaded into the register, and the write
data becomes valid and serial interface operation ends when SE goes LOW. Note that data will be corrupted if there are less than or more
than 16 clock pulses received during serial data transfer.
Register write (when OE is LOW)
OE
"L"
SE
DATA
R/W A2 A1 A0 - - - - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Register write (when OE is open-circuit)
OE ^"L"
(OPEN)
SE
DATA
CLK
OUT ^(Hi-Z)
R/W A2 A1 A0 - - - - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Analog Output Control (register write mode, OE = HIGH)
If OE is HIGH, serial interface operation starts when SE goes HIGH.
Write data comprises 1 read/write mode bit (write mode = 0), 3 address bits, and 4 dummy data bits transferred in sequence. The address
data becomes valid and serial interface operation ends when SE goes LOW. If the address data bits match the address control pin settings
(meaning the device is addressed), the output is enabled. If the output was already enabled and the address data does not match the address
pin settings, the output is disabled. Note that if there are less than or more than 8 clock pulses received during serial data transfer, an address
mismatch occurs and the output is disabled.
In addition, sequential write cycles to the register are permitted while OE is HIGH.
Register write (when OE is HIGH)
OE
SE
DATA
R/W A2 A1 A0 - - - -
CLK
1 2 3 4 56 7 8
OUT (Hi-Z)
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