SM5841H Datasheet, PDF (3/20 Pages) Nippon Precision Circuits Inc – Audio Multi-function Digital Filter

BLOCK DIAGRAM
SM5841H
LRCI
DIN BCKI
CKSL
CKI
CKO
RST
DSF1
DSF2
WSL1
WSL2
System
Clock
Timing
Controller
Deemphasis
Controler
Input/output
word length
selector
Input data Interface
Filter and Attenuation
Airthmetic block
Interface
Output date
OFST
WCKO
DOL
DOR
BCKO
VSS VDD
PIN DESCRIPTION
SOP DIP
Name
1
1
WSL1
8
6
WSL2
I/O¹
Input/output data select pins
Ip
WSL1
WSL2
HIGH
HIGH
HIGH
LOW
Ip
LOW
HIGH
LOW
LOW
Description
Noise shaper
Off
On
On
On
Input bit length
18 bits
18 bits
16 bits
16 bits
Output bit length
20 bits
18 bits
18 bits
16 bits
2
2
3
3
4
4
5
5
6
–
7
–
9
7
CKI
CKSL
CKO
VSS
NC
NC
DSF1
10 8
DSF2
Ip
System clock input
Ip
System clock select input. 384fs when HIGH, and 256fs when LOW.
O
System clock output. The CKI is first buffered before output on CKO.
–
Ground
–
No connection
–
No connection
Deemphasis select inputs
Ip
DSF1
DSF2
Deemphasis Sampling frequency
LOW
LOW
On
44.1 kHz
LOW
HIGH
On
48.0 kHz
HIGH
Ip
HIGH
LOW
HIGH
Off
–
On
32.0 kHz
11 9
12 10
RST
BCKO
Ip
System reset. Reset and initialization when RST is LOW.
O
Output bit clock
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