SM5841H Datasheet, PDF (15/20 Pages) Nippon Precision Circuits Inc – Audio Multi-function Digital Filter

SM5841H
System Reset and Output Muting (RST)
System reset
The SM5841H must be reset at power-ON by apply-
ing a LOW-level pulse on RST.
At system reset, the arithmetic and output timing
counters are reset on the next LRCI start edge, as
long as the CKI clock has already stabilized.
The power-ON reset pulse can be applied by a
microcontroller or, for systems where CKI and LRCI
are stable at power-ON, by connecting a 300 pF
capacitor between RST and VSS. For systems that do
not use a microcontroller, the capacitor must be cho-
sen such that the CKI and LRCI clocks fully stabilize
before RST goes from LOW to HIGH.
If the system clock is interrupted or is corrupted by
jitter, after power-ON reset and all internal timing is
synchronized, such that a timing error greater than
±3/8 × f_LRCI occurs, the internal timing is automati-
cally reset on the next LRCI start edge. This resyn-
chronization affects the internal operation and can
generate a momentary click noise output.
Output muting
When RST goes LOW, the DOL and DOR outputs
go LOW, immediately muting the output signal, and
they remain LOW for intervals in word units. Muting
is released and timing is synchronized on the 3rd ris-
ing edge of LRCI after RST goes HIGH. Note that
during muted output, the BCKO and WCKO clocks
do not stop.
RST
LRCI
(L)
1234
Internal reset
DOL
DOR
(L)
Figure 6. System reset timing and output muting
NIPPON PRECISION CIRCUITS—15