PXI-5404 Datasheet, PDF (4/6 Pages) National Instruments Corporation – 9 kHz to 105 MHz sine wave/DC to 100 MHz clock/1.07 μHz frequency resolution

100 MHz Frequency Generator
Specifications (continued)
As an Output
Sources for Output Signal ......................... 1. PXI_CLK10 (backplane connector)
2. Sample timebase clock (60 MHz)
divided by N (3 ≤ N ≤ 255)
3. REF IN (I/O panel SMB connector)
4. PXI_TRIG <0:7> (backplane connector)
5. PXI star trigger (backplane connector)
6. CLOCK output on CH 0
(I/O panel SMB connector)
7. Software trigger
8. Start trigger
Output Impedance ..................................... 50 Ω ± 5%
Output Protection ...................................... +6 to -1 V
VOH (Minimum)
Open load........................................ 4.0 V
50 Ω load......................................... 2.0 V
VOL (Maximum)
Open load........................................ 0.4 V
50 Ω load......................................... 0.2 V
Rise/Fall Time............................................. 4 ns
REF IN (Reference Input, I/O Panel Connector)
Connector .................................................. SMB
Frequency Range ....................................... 200 kHz to 30 MHz
Destinations .............................................. 1. PLL reference {refer to
"Phase-Lock Loop (PLL)"}
2. REF OUT (I/O panel SMB connector)
3. PFI 0 (I/O panel SMB connector)
4. PXI_TRIG <0:7> (backplane connector)
Input Impedance ........................................ 1 kΩ ±1%
Input Protection ......................................... 12 Vpp (sine or square wave) ±5 VDC
Amplitude................................................... 300 mVpp to 5 Vpp
Sine or square wave
Input Coupling............................................ AC
REF OUT (Reference Output, I/O Panel Connector)
Connector .................................................. SMB
Frequency Range ....................................... DC to 20 MHz
Sources ................................................... 1. PXI_CLK10 (backplane connector)
2. Sample timebase (60 MHz)
divided by N (3 ≤ N ≤ 255).
3. REF IN (I/O panel SMB connector)
4. PXI_TRIG <0:7> (backplane connector)
5. PXI star trigger (backplane connector)
6. CH 0 CLOCK output (I/O panel
SMB connector)
7. PFI 0 (I/O panel SMB connector)
8. Software trigger
9. Start trigger
Output Impedance ..................................... 50 Ω ±5 %, DC to 20 MHz
Output Protection ...................................... +6 to -1 V
VOH
Open load........................................ 4.0 V
50 Ω load......................................... 2.0 V
VOL
Open load........................................ 0.4 V
50 Ω load......................................... 0.2 V
Rise/Fall Time............................................. 4 ns
Triggers
Type ........................................................... Start trigger
Sources ...................................................... 1. PFI 0 ( I/O Panel SMB Connector )
2. PXI_TRIG<0:7> (backplane connector)
3. PXI star trigger (backplane connector)
4. Software (use function call)
5. Immediate (do not wait for a
trigger). Default.
Mode ................................................... Continuous
Trigger Detection ....................................... Edge (rising)
Pulse Width (Minimum) ............................. 10 ns
Trigger to SINE Output Delay .................... 250 µs, typical
Sample Clock
Frequency .................................................. 300 MS/s
Average Phase Noise Density
(PLL Reference set to REF IN) ............. -112 dBc/Hz
10 MHz SINE output
Offset 10 kHz ±500 Hz
Phase-Lock Loop (PLL)
PLL Reference Sources ............................. 1. PXI_CLK10 (backplane connector)
2. REF IN (I/O panel SMB connector)
3. PXI_TRIG <0:7> (backplane connector)
4. None (The PLL is not used. See
Internal Clock section). Default.
Frequency Accuracy .................................. When using the PLL, the frequency
accuracy of the NI PXI-5404 is solely
dependent on the frequency accuracy
of the PLL Reference Source.
Lock Time................................................... 200 ms, typical
PLL Reference Frequencies ...................... 3 to 20 MHz in 1 MHz increments
Frequency Locking Range ......................... ±50 ppm
PLL Reference Duty Cycles....................... 30 to 70%
Internal Clock
Clock Source .............................................. Clock circuitry can either be locked to
a reference signal using the PLL, or
use an onboard frequency reference
Frequency Accuracy .................................. ±2 ppm, typical for 15 to 35 ˚C
Calibrated at room temperature.
Frequency Temperature Coefficent ........... ±0.3 ppm /˚C
Multimodule Synchronization
Output skew of multiple NI 5404s ............ ±1 ns
Note: Two or more PXI-5404s can be
programmatically phase-aligned after
generation has started.
PLL Reference Frequencies for
Multimodule Synchronization ............... 3, 4, 5, 6, 10, 12, 15, or 20 MHz.
External Calibration (Factory Calibration)
Recommended Calibration Interval............ 1 year
Warm-up time ............................................ 15 minutes
Power Requirements
(SINE output, CLOCK output, and REF OUT generating maximum amplitude
waveforms into 50 loads).
+3.3 V ........................................................ 1000 mA
+5 V .......................................................... 550 mA
+12 V ........................................................ 180 mA
-12 V .......................................................... 50 mA
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